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CN-121985553-A - Multi-channel transistor and preparation method thereof

CN121985553ACN 121985553 ACN121985553 ACN 121985553ACN-121985553-A

Abstract

The disclosure provides a multichannel transistor and a preparation method thereof, and belongs to the field of power electronics. The multi-channel transistor comprises an epitaxial layer, an insulating layer, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial layer comprises a plurality of stacked heterojunctions, the top surface of the epitaxial layer is provided with a groove penetrating at least one heterojunction, the source electrode and the drain electrode are arranged on the epitaxial layer at intervals and are electrically connected with the heterojunctions, the insulating layer is at least arranged in the groove, the gate electrode is arranged on the surface, far away from the epitaxial layer, of the insulating layer and is arranged in the groove, and an n-type ion implantation area is further arranged on the epitaxial layer and is close to the groove. The embodiments of the present disclosure can fully exploit the advantages of high on-current density of multi-channel transistors.

Inventors

  • Chen Kuangli
  • WANG RUI
  • ZHANG ZHONGYU
  • JIANG ZHULIN

Assignees

  • 京东方华灿光电(广东)有限公司

Dates

Publication Date
20260505
Application Date
20251211

Claims (10)

  1. 1. A multi-channel transistor, characterized in that the multi-channel transistor comprises an epitaxial layer (10), an insulating layer (20), a gate electrode (31), a source electrode (32) and a drain electrode (33); the epitaxial layer (10) comprises a plurality of stacked heterojunctions (11), and the top surface of the epitaxial layer (10) is provided with a groove (12) at least penetrating one heterojunction (11); The source electrode (32) and the drain electrode (33) are positioned on the epitaxial layer (10) and are arranged at two sides of the groove (12) at intervals, and the source electrode (32) and the drain electrode (33) are electrically connected with each heterojunction (11); The insulating layer (20) is at least positioned in the groove (12), and the gate electrode (31) is positioned on the surface of the insulating layer (20) away from the epitaxial layer (10) and positioned in the groove (12); An n-type ion implantation region (13) is further arranged on the epitaxial layer (10), and the n-type ion implantation region (13) is close to the groove (12).
  2. 2. The multi-channel transistor according to claim 1, characterized in that in a cross section of the recess (12) parallel to the top surface of the epitaxial layer (10), the recess (12) extends from one side of the epitaxial layer (10) to the other side; Two n-type ion implantation regions (13) are arranged on the epitaxial layer (10), and the two n-type ion implantation regions (13) are respectively close to two opposite side walls of the groove (12).
  3. 3. A multi-channel transistor according to claim 2, characterized in that the n-type ion implantation region (13) has a width of 0.5 μm to 2 μm.
  4. 4. A multi-channel transistor according to claim 2, characterized in that the spacing of the two n-type ion implantation regions (13) is less than or equal to the width of the recess (12).
  5. 5. A multi-channel transistor according to claim 4, characterized in that the distance between two of the n-type ion implantation regions (13) is 0.5 μm to 2 μm, and the width of the recess (12) is 0.5 μm to 3 μm.
  6. 6. A multi-channel transistor according to any of claims 1 to 5, characterized in that the depth of the n-type ion implantation region (13) is greater than or equal to the depth of the recess (12).
  7. 7. A multi-channel transistor according to any of claims 1 to 5, characterized in that the number of layers of the heterojunction (11) is N, the recess (12) extending at most through the N-1 layer of the heterojunction (11).
  8. 8. A multi-channel transistor according to any of claims 1 to 5, characterized in that the distance of the source electrode (32) to the n-type ion implantation region (13) is less than or equal to the distance of the drain electrode (33) to the n-type ion implantation region (13).
  9. 9. A method of fabricating a multi-channel transistor, the method comprising: Forming an epitaxial layer on a substrate, the epitaxial layer comprising a plurality of stacked heterojunctions; implanting n-type ions into the top surface of the epitaxial layer to form an n-type ion implantation region; Forming a source electrode and a drain electrode on the epitaxial layer, wherein the source electrode and the drain electrode are electrically connected with each heterojunction; Forming a groove on the top surface of the epitaxial layer, wherein the groove at least penetrates through one heterojunction, the source electrode and the drain electrode are arranged on two sides of the groove in an electrode-to-electrode arrangement mode, and the n-type ion implantation area is close to the groove; Forming an insulating layer in the groove; And forming a gate electrode on the surface of the insulating layer, which is far away from the epitaxial layer, wherein the gate electrode is positioned in the groove.
  10. 10. The method of claim 9, wherein implanting n-type ions on the top surface of the epitaxial layer comprises: Controlling the power of the ion implanter to be 20KeV to 200KeV, controlling the beam current to be 1mA to 30mA, controlling the n-type doping amount to be 10 13 cm -2 to 10 15 cm -2 , and forming the n-type ion implantation region on the top surface of the epitaxial layer.

Description

Multi-channel transistor and preparation method thereof Technical Field The present disclosure relates to the field of power electronics, and more particularly, to a multi-channel transistor and a method of fabricating the same. Background Gallium nitride as a third generation wide bandgap semiconductor material exhibits significant advantages in high frequency, high power electronic devices due to its excellent physical and electrical properties, such as high electron mobility, high thermal stability, and wide bandgap. As an extension of the structure of a high electron mobility transistor, a multi-channel transistor has received attention in recent years. In the related art, a multi-channel transistor includes a multi-layered stacked AlGaN/GaN heterojunction, and a plurality of parallel two-dimensional electron gas (2 DEG) channels are introduced by stacking a plurality of heterojunctions, so that carrier density per unit area can be increased, thereby enhancing current driving capability of the transistor and reducing on-resistance. However, as the number of heterojunction layers increases, the distance between the gate and the underlying channel increases, resulting in reduced control capability of the gate to the channel, requiring more complex gate structures, and limiting the fabrication efficiency of the multi-channel transistor. Disclosure of Invention The embodiment of the disclosure provides a multi-channel transistor and a preparation method thereof, which can solve the problem of high difficulty in gate control in the multi-channel transistor. The technical scheme is as follows: In one aspect, the embodiment of the disclosure provides a multi-channel transistor, which comprises an epitaxial layer, an insulating layer, a gate electrode, a source electrode and a drain electrode, wherein the epitaxial layer comprises a plurality of stacked heterojunctions, the top surface of the epitaxial layer is provided with a groove penetrating at least one heterojunction, the source electrode and the drain electrode are arranged on the epitaxial layer at intervals and are electrically connected with the heterojunctions, the insulating layer is at least positioned in the groove, the gate electrode is positioned on the surface, far away from the epitaxial layer, of the insulating layer and is positioned in the groove, and an n-type ion implantation region is further arranged on the epitaxial layer and is close to the groove. In one implementation of the disclosure, in a cross section of the groove parallel to the top surface of the epitaxial layer, the groove extends from one side edge of the epitaxial layer to the other side edge, and two n-type ion implantation regions are arranged on the epitaxial layer and are respectively close to two opposite side walls of the groove. In another implementation of the present disclosure, the n-type ion implantation region has a width of 0.5 μm to 2 μm. In another implementation of the present disclosure, a distance between two of the n-type ion implantation regions is smaller than or equal to a width of the recess. In another implementation of the present disclosure, a pitch of two of the n-type ion implantation regions is 0.5 μm to 2 μm, and a width of the recess is 0.5 μm to 3 μm. In another implementation of the present disclosure, the depth of the n-type ion implantation region is greater than or equal to the depth of the recess. In another implementation of the present disclosure, the number of layers of the heterojunction is N, and the grooves extend through at most the N-1 layers of the heterojunction. In another implementation of the present disclosure, a distance from the source electrode to the n-type ion implantation region is less than or equal to a distance from the drain electrode to the n-type ion implantation region. On the other hand, the embodiment of the disclosure provides a preparation method of a multi-channel transistor, which comprises the steps of forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a plurality of stacked heterojunctions, implanting n-type ions into the top surface of the epitaxial layer to form n-type ion implantation regions, forming a source electrode and a drain electrode on the epitaxial layer, wherein the source electrode and the drain electrode are electrically connected with the heterojunctions, forming a groove on the top surface of the epitaxial layer, the groove at least penetrates through one heterojunction, the source electrode and the drain electrode are arranged on two sides of the groove in an electrode-gap mode, the n-type ion implantation regions are close to the groove, an insulating layer is formed in the groove, and a gate electrode is formed on the surface, far away from the epitaxial layer, of the insulating layer and is located in the groove. Optionally, implanting n-type ions on the top surface of the epitaxial layer comprises controlling the power of an ion implanter to be 20KeV