CN-121985555-A - Deep source electrode etched wide bandgap transistor and manufacturing method thereof

CN121985555ACN 121985555 ACN121985555 ACN 121985555ACN-121985555-A

Abstract

The invention belongs to the technical field of semiconductor devices, and discloses a deep source etching wide band gap transistor and a preparation method thereof, which aim at the problem that the existing wide band gap transistor is easy to burn out by single particles, the upper surface both ends of basic component are provided with source and drain electrode respectively, are provided with the grid between source and the drain electrode, and the sculpture has recess or through-hole between source and the basic component, recess or through-hole contact with basic component. On the basis of the traditional structure, the ohmic metal of the source electrode is deposited by etching the lower part of the source electrode to the buffer layer area of the HEMT device or the bulk material area of the MISFET device in an electron beam evaporation, sputtering or electroplating mode, and the source electrode metal is in contact with the buffer layer or the substrate. The source electrode can extract holes below the grid electrode, so that hole accumulation in the device is reduced, the single particle burning risk of the device is reduced, and the single particle resistance of the device is improved.

Inventors

ZHAO SHENGLEI
Gao Linhuan
SONG XIUFENG
WANG ZHONGXU
YU LONGYANG
ZHANG JINCHENG
HAO YUE

Assignees

西安电子科技大学
陕西君普新航科技有限公司

Dates

Publication Date: 20260505
Application Date: 20260121

Claims (10)

1. The deep source electrode etched wide band gap transistor is characterized by comprising a base component, wherein a source electrode and a drain electrode are respectively arranged at two ends of the upper surface of the base component, a grid electrode is arranged between the source electrode and the drain electrode, a groove or a through hole is etched between the source electrode and the base component, and the groove or the through hole is in contact with the base component.
2. The deep source etched wide bandgap transistor of claim 1, wherein said base member comprises a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked in sequence from top to bottom, and said source and drain electrodes are disposed at respective ends of said barrier layer.
3. The deep source etched wide bandgap transistor of claim 2, wherein the upper surface of the barrier layer is further provided with a p-GaN layer and a passivation layer, the p-GaN layer being located between the source and drain electrodes, the gate electrode being disposed on the upper surface of the p-GaN layer, the passivation layer being disposed between the p-GaN layer and the source electrode and between the p-GaN layer and the drain electrode.
4. The deep source etched wide bandgap transistor of claim 3, wherein said recess is etched in said barrier layer, and wherein said recess bottom extends into said buffer layer and contacts said buffer layer, said source is located at said top of said recess, and said deep source is located in said recess.
5. The deep source etched wide bandgap transistor of claim 3, wherein said via is etched in said barrier layer and has a bottom penetrating said substrate side, a source located at said top of said via, and a deep source located inside said via.
6. The deep source etched wide bandgap transistor of claim 2, wherein the upper surface of the barrier layer is further provided with a passivation layer, the gate is disposed on the upper surface of the barrier layer, the passivation layer is disposed between the gate and the source and between the gate and the drain; The recess sculpture is in barrier layer upper surface, and the recess bottom extends to the buffer layer inside to with the buffer layer contact, the source electrode is located the top of recess, the inside of recess is provided with dark source electrode.
7. The deep source electrode etched wide bandgap transistor of claim 2, wherein the upper surface of the barrier layer is further provided with a gate dielectric layer and a passivation layer in sequence from top to bottom, the gate is arranged on the upper surface of the gate dielectric layer, and the passivation layer is arranged between the gate and the source and between the gate and the drain; The recess sculpture is in barrier layer upper surface, and the recess bottom extends to the buffer layer inside to with the buffer layer contact, the source electrode is located the top of recess, the inside of recess is provided with dark source electrode.
8. The deep source electrode etched wide bandgap transistor of claim 1, wherein the base assembly comprises a substrate and a gate dielectric layer which are sequentially stacked from top to bottom, a source electrode and a drain electrode are respectively arranged at two ends of the upper surface of the substrate, a gate electrode is arranged on the upper surface of the gate dielectric layer, and passivation layers are respectively arranged between the gate electrode and the source electrode and between the gate electrode and the drain electrode; The groove is etched on the upper surface of the substrate, the bottom of the groove extends to the inside of the substrate and is in contact with the substrate, the source electrode is located at the top of the groove, and a deep source electrode is arranged inside the groove.
9. A method of manufacturing a deep source etched wide bandgap transistor according to any of claims 1-8, comprising the steps of: S1, preparing a basic component; S2, etching the area except the upper surface area of the foundation assembly to be reserved under the protection gas by adopting an inductively coupled plasma etching process, and exposing the left side surface and the right side surface of the upper surface of the foundation assembly; S3, etching a groove or a through hole on the left side surface of the upper surface of the base component, enabling the groove or the through hole to be in contact with the base component, manufacturing a mask, and depositing a deep source electrode in the groove or the through hole by adopting an electron beam evaporation, sputtering or electroplating process; S4, respectively manufacturing masks of a source electrode and a drain electrode on the left side surface and the right side surface of the upper surface of the basic component, and then depositing the source electrode and the drain electrode by adopting an electron beam evaporation or sputtering process; S5, manufacturing a mask on the upper surface of the basic component, then adopting an electron beam evaporation or sputtering process to deposit a grid electrode, and adopting a plasma enhanced chemical vapor deposition process to deposit a passivation layer between the grid electrode and the source electrode and between the grid electrode and the drain electrode; and S6, opening holes in the passivation layer, and leading out electrodes to obtain the deep source electrode etched wide band gap transistor.
10. The method of claim 9, wherein in S3, the thickness of the metal of the deep source is 10 nm-10 μm, and in S5, the thickness of the passivation layer is 10 nm-10 μm.

Description

Deep source electrode etched wide bandgap transistor and manufacturing method thereof Technical Field The invention belongs to the technical field of semiconductor devices, and particularly relates to a deep source electrode etched wide bandgap transistor and a manufacturing method thereof. Background The space irradiation damage of the electronic device is one of important factors affecting the long-term reliable operation of the spacecraft in orbit. The irradiation effect mechanism of the electronic device and the test technology are mainly used for researching the generation, evolution, response process and experimental method of irradiation damage, are the basis for improving the irradiation resistance of the device, and the irradiation resistance reinforcing technology of the aerospace device has been a hot spot problem focused in academia and industry for a long time. In recent years, along with the development of aerospace industry in China, the development of high-performance and high-reliability anti-radiation power devices becomes one of key technologies in the aerospace field. Gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium oxide (Ga 2O3), silicon carbide (SiC) and the like are used as wide forbidden band semiconductor materials, so that the limit of the traditional Si device is broken through, and the silicon nitride semiconductor material is more suitable for extreme environments such as high temperature, high voltage and radiation than the traditional Si device. Based on the application of the wide forbidden band semiconductor material in the field of aerospace, the problem of space radiation effect and device reliability is particularly important. However, conventional wide bandgap transistors, due to the lack of efficient carrier regulation mechanisms, induce large amounts of unbalanced carriers when heavy ions are incident. Under the action of an electric field in the device, electrons are transported to a drain region with a high electric field and a high potential, holes accumulate below a grid electrode, so that the threshold voltage of the device is shifted, the source and drain of the device are penetrated in an off state, further electric leakage is increased, and finally, the device is burnt out (SINGLE EVENT Burnout, SEB) to fail. At present, the single particle burning voltage of the wide band gap transistor is still lower, and the application of the wide band gap power device in the strong radiation extreme environments such as aerospace and the like is limited. The existing single particle reinforcement technology generally comprises two types, namely, one type is to optimize the epitaxial structure of the device, enhance charge recombination and inhibit defects, such as introducing a composite buffer layer between an AlGaN barrier layer and a GaN channel layer, and constructing stepped potential distribution, so that unbalanced carriers generated by single particles are quickly recombined, and meanwhile, the generation of defect states is inhibited, and the single particle burning-out resistance voltage of the device is further improved. The other is to optimize the structure of the field plate and the terminal, reduce the local high field effect, and disperse the peak electric field near the drain electrode to a larger area by adopting the source field plate, the drain field plate or the composite field plate structure, so as to reduce the electric field intensity. In addition, through the structures such as gradual change doping, field limiting rings, superjunctions and the like of the terminal area, the electric field distribution at the edge of the device can be further optimized, and avalanche breakdown and carrier multiplication effects caused by high fields after single particle incidence are avoided. However, the method for optimizing the epitaxial structure of the device has extremely high requirements on the control precision of parameters such as material component proportion, epitaxial layer thickness, lattice matching and the like, and once tiny deviation occurs, the epitaxial layer is cracked and other defects are caused, so that the irradiation resistance is degraded, the whole electrical performance of the device is influenced, and even the yield of the device is reduced. The adoption of the field plate structure can modulate the surface peak electric field, but has small effect on irradiation charges generated by the buffer layer and the channel layer in the device, can only improve the irradiation resistance problem related to the surface electric field, has limited effect on improving the single particle burnout threshold, and is difficult to cope with the high-intensity irradiation environment. The field limiting ring, the superjunction and other structures have strict requirements on the uniformity of doping concentration and region distribution, and meanwhile, multiple steps of doping and photoetching steps are addit