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CN-121985556-A - GaN HEMT device with PIN junction control gate source bridge and preparation method thereof

CN121985556ACN 121985556 ACN121985556 ACN 121985556ACN-121985556-A

Abstract

The invention belongs to the technical field of power semiconductors, and relates to a GaN HEMT device with a PIN junction control gate source bridge and a preparation method thereof. Compared with the traditional Schottky p-GaN gate, the PIN junction gate has the main characteristics that the surface electric field of the gate is reduced, the gate leakage current is inhibited, and the gate breakdown voltage of the device is greatly improved. Meanwhile, a PIN junction is introduced to control a gate-source bridge structure, the switching state of a gate-source bridge channel is controlled by changing the mutual depletion action of a gate voltage regulation PIN junction, a release path without barrier blocking is provided for stored charges, and the purpose of enhancing the stability of threshold voltage is achieved. In addition, the design structure also realizes decoupling of threshold voltage and reverse conduction voltage, has the process and manufacture procedure approximately same as that of the traditional Schottky p-GaN gate HEMT device, is compatible in process and easy to realize.

Inventors

  • ZHAO ZHIJIA
  • WEI JIE
  • Luo Benfa
  • DENG GAOQIANG
  • LUO XIAORONG

Assignees

  • 电子科技大学

Dates

Publication Date
20260505
Application Date
20260130

Claims (6)

  1. 1. A GaN HEMT device with a PIN junction control gate source bridge comprises a substrate (1), a buffer layer (2), a channel layer (3) and a barrier layer (4) which are sequentially stacked from bottom to top along the vertical direction of the device, wherein a first conductive material (91) and a fourth conductive material (92) are respectively arranged at two ends of the upper surface of the device, the first conductive material (91) and the fourth conductive material (92) penetrate through the barrier layer (4) along the vertical direction and then are embedded into the upper layer of the channel layer (3), and the GaN HEMT device is characterized in that the upper surface of the barrier layer (4) between the first conductive material (91) and the fourth conductive material (92) is provided with a p-GaN layer (5), a first n-GaN layer (6) and a second n-GaN layer (7) which are sequentially stacked from bottom to top, wherein the middle part of the p-GaN layer (5) extends to be connected with the first conductive material (91) along the transverse direction of the device, the p-GaN layer (5) and the first conductive material (91) are connected into an I shape in the top view, the first n-GaN layer (6) and the second n-GaN layer (7) extends to the first conductive material (91) along the transverse direction of the device, the first n-GaN layer (6) and the second n-GaN layer (7) are in a convex shape, the device surface between the first conductive material (91) and the fourth conductive material (92) is covered with a dielectric passivation layer (8), namely the dielectric passivation layer (8) covers the upper surface of the barrier layer (4), the surface of the p-GaN layer (5), the side surface of the first n-GaN layer (6) and the surface of the second n-GaN layer (7), the second conductive material (101) is arranged on the upper surface of the first conductive material (91), the second conductive material (101) is extended to be in contact with the upper surface of the p-GaN layer (5) along the side surface of the first conductive material (91) to form a convex structure, the convex structure is extended towards the direction close to the p-GaN layer (5) along the transverse direction of the device, the width of the convex structure along the longitudinal direction of the device is smaller than the width of the connecting part of the p-GaN layer (5) and the first conductive material (91) along the longitudinal direction of the device, the third conductive material (102) is arranged on the second n-GaN layer (7), the third conductive material (102) is isolated from the upper surface of the p-GaN layer (5) along the longitudinal direction of the device, the third conductive material (102) is in a top view, the rest of the third conductive material (102) penetrates through the dielectric passivation layer (8) and is in contact with the second n-GaN layer (7); The first conductive material (91) forms ohmic contact with the channel layer (3), the second conductive material (101) forms ohmic contact with the p-GaN layer (5) to lead out a source electrode, the third conductive material (102) forms Schottky contact with the second n-GaN layer (7) to lead out a grid electrode, and the fourth conductive material (92) forms ohmic contact with the channel layer (3) to lead out a drain electrode.
  2. 2. A GaN HEMT device with PIN junction control gate source bridge according to claim 1, characterized in that the concentration of the second n-GaN layer (7) is greater than the concentration of the first n-GaN layer (6).
  3. 3. The GaN HEMT device with PIN junction control gate source bridge of claim 1, wherein the substrate (1) is made of one of sapphire and Si, siC, alN, gaN, alGaN, znO, gaAs.
  4. 4. The GaN HEMT device with PIN junction control gate source bridge of claim 1, wherein the barrier layer (4) is made of one or a combination of several materials of AlN, alGaN, inGaN, inAlN.
  5. 5. The GaN HEMT device with the PIN junction control gate source bridge according to claim 1, wherein the dielectric passivation layer (8) is made of one of SiN x 、SiO 2 、Al 2 O 3 and AlN.
  6. 6. A method for manufacturing a GaN HEMT device with a PIN junction control gate source bridge, for the GaN HEMT device with a PIN junction control gate source bridge of any one of claims 1-5, comprising the steps of: Step 1, preparing a substrate (1), wherein a buffer layer (2) is epitaxially arranged on the substrate, a channel layer (3) is epitaxially arranged on the buffer layer (2), a barrier layer (4) is epitaxially arranged on the channel layer (3), a p-GaN layer (5) is epitaxially arranged on the barrier layer (4), a first n-GaN layer (6) is epitaxially arranged on the p-GaN layer (5), and a second n-GaN layer (7) is epitaxially arranged on the first n-GaN layer (6); step 2, partially etching the p-GaN layer (5), the first n-GaN layer (6) and the second n-GaN layer (7) by adopting an etching process, and reserving a grid part and a part connected with a source electrode; Step 3, partially etching the first n-GaN layer (6) and the second n-GaN layer (7) on the p-GaN layer (5) and the source electrode connecting part by adopting an etching process; Step 4, forming a dielectric passivation layer (8) by adopting a chemical vapor deposition process; etching two ends of the medium passivation layer (8) by adopting an etching process, exposing a source electrode hole and a drain electrode hole at two ends of the channel layer (3), depositing metal, forming a first conductive material (91) and a fourth conductive material (92) by adopting a stripping process, and then carrying out rapid thermal annealing; Depositing metal, forming a second conductive material (101) above the first conductive material (91) and the p-GaN layer (5) on the side close to the source electrode by adopting a stripping process, and then performing rapid thermal annealing; And 7, etching the dielectric passivation layer (8) above the second n-GaN layer (7) by adopting an etching process, depositing metal and adopting a stripping process to form a third conductive material (102).

Description

GaN HEMT device with PIN junction control gate source bridge and preparation method thereof Technical Field The invention belongs to the technical field of power semiconductors, and relates to a GaN HEMT device with a PIN junction control gate source bridge and a preparation method thereof. Background Due to the charge storage effect, the conventional schottky p-GaN gate HEMT device has a problem of serious drift of threshold voltage. In order to solve the problem, the current solution is to adopt ohmic p-GaN gate, schottky ohmic mixed gate and single gate source bridge, so that the potential of the p-GaN gate is not floated any more, and a release path without barrier is provided for storing charges. However, this also provides a path for gate leakage current, resulting in increased gate leakage current and impaired device gate withstand voltage. In addition, the traditional Schottky p-GaN gate HEMT device also has the problems of smaller gate breakdown voltage, narrower gate voltage safety window and incompatible gate driving voltage. Disclosure of Invention The invention provides a GaN HEMT device with a PIN junction control gate source bridge and a preparation method thereof based on the application requirement of a Schottky p-GaN gate HEMT device. Compared with the traditional Schottky p-GaN gate, the PIN junction gate has the advantages that the electric field on the surface of the gate is reduced, the gate leakage current is restrained, and the gate breakdown voltage of the device is greatly improved. Meanwhile, a PIN junction is introduced to control a gate-source bridge structure, the switching state of a gate-source bridge channel is controlled by changing the mutual depletion action of a gate voltage regulation PIN junction, and the threshold voltage stability is greatly enhanced while a new gate leakage current path is not added. In order to achieve the above object, the present invention has the following technical scheme: 1. The GaN HEMT device with the PIN junction control gate source bridge comprises a substrate 1, a buffer layer 2, a channel layer 3 and a barrier layer 4 which are sequentially stacked from bottom to top along the vertical direction of the device, wherein a first conductive material 91 and a fourth conductive material 92 are respectively arranged at two ends of the upper surface of the device, and the first conductive material 91 and the fourth conductive material 92 penetrate through the barrier layer 4 along the vertical direction and then are embedded into the upper layer of the channel layer 3; the device is characterized in that a p-GaN layer 5, a first n-GaN layer 6 and a second n-GaN layer 7 which are sequentially stacked from bottom to top are arranged on the upper surface of a barrier layer 4 between a first conductive material 91 and a fourth conductive material 92, wherein the middle part of the p-GaN layer 5 extends along the transverse direction of the device to be connected with the first conductive material 91, the p-GaN layer 5 and the first conductive material 91 are connected to form an I shape in a top view of the device, the middle parts of the first n-GaN layer 6 and the second n-GaN layer 7 extend towards the first conductive material 91 along the transverse direction of the device, but have a distance from the first conductive material 91, the first n-GaN layer 6 and the second n-GaN layer 7 are in a convex shape in the top view of the device, the surface of the device between the first conductive material 91 and the fourth conductive material 92 is covered with a medium passivation layer 8, namely the medium passivation layer 8 covers the upper surface of the first conductive material 91, the surface of the p-GaN layer 5, the side surface of the first n-GaN layer 6 and the second n-GaN layer 7 are connected to form a convex structure on the upper surface of the first conductive material 101 and the second conductive material 101 is contacted with the first conductive material 101, the second n-GaN layer 7 is provided with a third conductive material 102, in a top view of the device, the third conductive material 102 is in a convex shape, the outer side of the third conductive material 102 is isolated from the second n-GaN layer 7 by a medium passivation layer 8, and the rest of the third conductive material 102 penetrates through the medium passivation layer 8 to be in contact with the second n-GaN layer 7; The first conductive material 91 forms ohmic contact with the channel layer 3, the second conductive material 101 forms ohmic contact with the p-GaN layer 5 to lead out a source electrode, the third conductive material 102 forms Schottky contact with the second n-GaN layer 7 to lead out a gate electrode, and the fourth conductive material 92 forms ohmic contact with the channel layer 3 to lead out a drain electrode. Preferably, the concentration of the second n-GaN layer 7 is greater than the concentration of the first n-GaN layer 6. Preferably, th