CN-121985558-A - Ferroelectric transistor and preparation method and application thereof

CN121985558ACN 121985558 ACN121985558 ACN 121985558ACN-121985558-A

Abstract

The invention relates to the technical field of semiconductor devices and provides a ferroelectric transistor and a preparation method and application thereof, wherein the preparation method of the ferroelectric transistor comprises the following steps of firstly forming a semiconductor layer on a substrate, performing patterning and etching through a photoetching process, and thermally oxidizing the semiconductor layer at a preset temperature to enable the semiconductor layer to be in situ converted into a ferroelectric layer to form a hetero-structure of the semiconductor layer and the ferroelectric layer; then photo-etching exposure source and drain electrode pattern, depositing metal by electron beam or thermal evaporation and combining with Lift-off process to complete source and drain electrode patterning, preparing dielectric layer on ferroelectric layer by atomic layer deposition method, and finally photo-etching exposure top electrode pattern, and completing top electrode preparation by evaporation and Lift-off process. The method realizes an atomic-level ultra-flat uniform interface, can effectively inhibit the adverse effect of an interface defect state and a depolarization field on ferroelectric performance, and ensures that the device has the advantages of low working voltage, high fatigue resistance and high-speed response, and simultaneously has low thermal budget, high process compatibility and high expandability, and the overall device performance is excellent.

Inventors

PENG HAILIN
WU QINCI
LIU HONGTAO
HAN BINGCHEN
LI ZHONGRUI

Assignees

北京大学

Dates

Publication Date: 20260505
Application Date: 20251211

Claims (13)

1. A method of fabricating a ferroelectric transistor, comprising the steps of: Forming a semiconductor layer on a substrate; patterning and etching the semiconductor layer by a photolithography process; performing thermal oxidation on the patterned and etched semiconductor layer at a preset temperature, and converting the patterned and etched semiconductor layer into a ferroelectric layer in situ to form a heterostructure of the ferroelectric layer and the semiconductor layer; Exposing the source electrode and the drain electrode patterns of the ferroelectric transistor through a photoetching process, depositing to form the source electrode and the drain electrode by utilizing an electron beam evaporation or thermal evaporation method, and finishing the patterning of the source electrode and the drain electrode through a Lift-off process; Forming a dielectric layer on the ferroelectric layer by layer through an atomic layer deposition process; After exposing the top electrode pattern of the ferroelectric transistor on the dielectric layer by a photoetching process, depositing to form a top electrode by an electron beam evaporation or thermal evaporation method, and finishing the top electrode patterning by a Lift-off process.
2. The method of manufacturing a ferroelectric transistor according to claim 1, comprising the steps of, when forming a semiconductor layer on the substrate: bi 2 Se 3 is used as a Bi source and a Se source, oxygen is introduced as an oxygen source, a continuous semiconductor layer film is obtained through growth at 400-600 ℃, and the thickness of the film is controlled to be 2-20nm; Or preparing Bi 2 O 2 Se doped with Zn or Cu by using ion implantation equipment to obtain the p-type semiconductor layer.
3. The method of manufacturing a ferroelectric transistor according to claim 1, wherein patterning and etching are performed on the semiconductor layer, comprising the steps of: Spin-coating photoresist on the semiconductor layer, and completing pattern exposure and development through a photolithography process; And etching the exposure area by a sulfuric acid and hydrogen peroxide wet method for 3-10s to form a channel pattern, and completing the patterning of the semiconductor layer.
4. The method of manufacturing a ferroelectric transistor according to claim 1, wherein the semiconductor layer is converted into the ferroelectric layer in situ, comprising the steps of: Oxidizing the upper layer of the semiconductor layer into a Bi 2 SeO 5 ferroelectric layer by a high-temperature thermal oxidation mode, wherein the oxidation is carried out in air or O 2 atmosphere, the oxidation temperature is 300-500 ℃, the pressure is controlled to be 0.01-1atm, the ferroelectric layer is formed on the upper layer, the semiconductor layer is in a heterostructure under the ferroelectric layer, and the thickness of the ferroelectric layer is controlled to be 1-10nm.
5. The method of manufacturing a ferroelectric transistor according to claim 1, further comprising the steps of, before forming a semiconductor layer on the substrate: Sequentially using acetone, isopropanol and deionized water to ultrasonically clean the substrate so as to remove organic matters and particle pollution on the substrate; And drying the cleaned substrate in a nitrogen environment.
6. A ferroelectric transistor manufactured by the method of manufacturing a ferroelectric transistor according to any one of claims 1 to 5, the ferroelectric transistor comprising: A substrate; A semiconductor layer formed on the substrate; a ferroelectric layer formed on the semiconductor layer; A source electrode and a drain electrode disposed on opposite ends of the semiconductor layer and the ferroelectric layer; a dielectric layer formed on a side of the ferroelectric layer, the source electrode, and the drain electrode facing away from the substrate; and a top electrode formed on the dielectric layer.
7. The ferroelectric transistor according to claim 6, wherein the material of the semiconductor layer is Bi 2 O 2 Se or any one of Bi 2 O 2 Se doped with Zn or Cu, and the thickness of the semiconductor layer is 2 to 20nm.
8. The ferroelectric transistor according to claim 6, wherein the ferroelectric layer is Bi 2 SeO 5 , and the ferroelectric layer has a thickness of 1-10nm.
9. The ferroelectric transistor according to claim 6, wherein the material of the source electrode or the drain electrode is any one of Ti, pd, cr, and Au, and the thickness of the source electrode or the drain electrode is 20 to 100nm.
10. The ferroelectric transistor according to claim 6, wherein the material of the dielectric layer is any one of HfO 2 、Al 2 O 3 and SiO 2 , and the thickness of the dielectric layer is 2-10nm.
11. The ferroelectric transistor according to claim 6, wherein the material of the top electrode is any one of W, tiN, au, pt and Cu, and the thickness of the top electrode is 20-100nm.
12. Use of a ferroelectric transistor according to any one of claims 6-11 for a non-volatile memory array, each cell being constituted by one of said ferroelectric transistors for achieving high density interconnection integration.
13. Use of a ferroelectric transistor according to any one of claims 6 to 11 for storing a monolithic ferroelectric transistor array structure, each cell being formed by an integration of one transistor and one of said ferroelectric transistors.

Description

Ferroelectric transistor and preparation method and application thereof Technical Field The invention relates to the technical field of semiconductor devices, in particular to a ferroelectric transistor and a preparation method and application thereof. Background Data-centric applications such as Artificial Intelligence (AI) and internet of things (IoT) are emerging, which place stringent demands on high-performance data storage and processing systems that must be high-speed, high-density, and energy-efficient at the same time, and further place more stringent technical demands on non-volatile memory devices in terms of high-density, low-power consumption, and high reliability. As a powerful candidate for next generation embedded non-volatile memories and in-memory computing architectures, ferroelectric transistors integrate ferroelectric layers with semiconductor channels, with significant advantages of high speed, low power consumption, non-destructive readout, etc. Among them, hafnium oxide (HfO 2) -based ferroelectric transistors are being widely focused and studied due to their excellent compatibility with Complementary Metal Oxide Semiconductor (CMOS) processes. But the HfO 2 -based ferroelectric transistor still faces key bottlenecks such as poor wafer level uniformity, depolarization of an interface, performance degradation caused by critical dimension effect and the like, the thermal budget of the current HfO 2 -based ferroelectric film is generally high (usually more than or equal to 400 ℃) so as to severely limit the compatibility with a back end interconnection (BEOL) process, and in addition, more defects exist at the interface of the HfO 2 -based ferroelectric material and the conventional silicon-based or two-dimensional semiconductor channel, charge trapping and trap generation can be caused, and the reliability of the device is obviously reduced. The introduction and optimization of an Interface Layer (IL) between a ferroelectric material and a semiconductor channel is one of the effective ways to improve the interface quality. However, the interfacial layer itself shares a portion of the applied voltage, thereby impeding further reduction of the operating voltage. Therefore, the realization of integration of ultra-thin ferroelectric materials with atomically flat interfaces with semiconductor materials is critical to improving the performance of ferroelectric field effect transistors. Disclosure of Invention The invention provides a ferroelectric transistor and a preparation method and application thereof, which are used for solving the defects of high working voltage, poor durability and poor process compatibility of a ferroelectric transistor system in the prior art, realizing an atomic-level ultra-flat and uniform interface, effectively inhibiting the adverse effect of an interface defect state and a depolarization field on the ferroelectric performance of a device, having the advantages of low working voltage, high fatigue resistance, high speed and the like, and simultaneously having low thermal budget, high process compatibility, high expandability and excellent device performance. The invention provides an equipping method of a ferroelectric transistor, which comprises the following steps: Forming a semiconductor layer on a substrate; patterning and etching the semiconductor layer by a photolithography process; performing thermal oxidation on the patterned and etched semiconductor layer at a preset temperature, and converting the patterned and etched semiconductor layer into a ferroelectric layer in situ to form a heterostructure of the ferroelectric layer and the semiconductor layer; Exposing the source electrode and the drain electrode patterns of the ferroelectric transistor through a photoetching process, depositing to form the source electrode and the drain electrode by utilizing an electron beam evaporation or thermal evaporation method, and finishing the patterning of the source electrode and the drain electrode through a Lift-off process; Forming a dielectric layer on the ferroelectric layer by layer through an atomic layer deposition process; After exposing the top electrode pattern of the ferroelectric transistor on the dielectric layer by a photoetching process, depositing to form a top electrode by an electron beam evaporation or thermal evaporation method, and finishing the top electrode patterning by a Lift-off process. According to the preparation method of the ferroelectric transistor provided by the invention, when a semiconductor layer is formed on the substrate, the preparation method comprises the following steps: bi 2Se3 is used as a Bi source and a Se source, oxygen is introduced as an oxygen source, a continuous semiconductor layer film is obtained through growth at 400-600 ℃, and the thickness of the film is controlled to be 2-20nm; Or preparing Bi 2O2 Se doped with Zn or Cu by using ion implantation equipment to obtain the p-type semiconductor layer. Accordi