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CN-121985560-A - MOSFET device

CN121985560ACN 121985560 ACN121985560 ACN 121985560ACN-121985560-A

Abstract

The invention relates to the technical field of transistors, in particular to a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device, which comprises a semiconductor substrate and a grid electrode, wherein the semiconductor substrate comprises an active region, the grid electrode is positioned at one side of the semiconductor substrate, the grid electrode comprises a first strip-shaped sub-grid, a second strip-shaped sub-grid and a grid block, one end of the first strip-shaped sub-grid is connected with the second strip-shaped sub-grid to form a corner, the grid block is positioned at least one corner and positioned in the active region, the active region comprises a channel region, a source region and a drain region, the channel region is positioned below the first strip-shaped sub-grid and the grid block, and the source region and the drain region are respectively positioned at two sides of the channel region. The arrangement of the grid block can offset the influence of the non-uniform doping of the channel edge region on the performance of the device to a certain extent, and the performance and stability of the device are improved.

Inventors

  • LIU JUNWEN

Assignees

  • 无锡芯卓湖光半导体有限公司

Dates

Publication Date
20260505
Application Date
20260205

Claims (10)

  1. 1. A MOSFET device, comprising: A semiconductor substrate including an active region; The grid electrode comprises a first strip-shaped sub-grid, a second strip-shaped sub-grid and a grid block, wherein one end of the first strip-shaped sub-grid is connected with the second strip-shaped sub-grid to form a corner, the grid block is positioned at least at one corner and in the active region, the active region comprises a channel region, a source region and a drain region, the channel region is positioned below the first strip-shaped sub-grid and the grid block, and the source region and the drain region are respectively positioned at two sides of the channel region.
  2. 2. The MOSFET device of claim 1, wherein said gate block comprises a bevel bridging between said first strip-like sub-gate and said second strip-like sub-gate, said bevel being any one of a concave cambered surface, a convex cambered surface, or a flat cambered surface.
  3. 3. The MOSFET device of claim 1, wherein said gate block comprises a folded surface bridging between said first strip-like sub-gate and said second strip-like sub-gate, said folded surface comprising a first connection surface and a second connection surface connected.
  4. 4. A MOSFET device according to claim 3, characterized in that the first connection face and the second connection face are planar faces, the angle between the first connection face and the direction of extension of the second strip-like sub-gate being greater than or equal to 90 °, the angle between the second connection face and the direction of extension of the first strip-like sub-gate being greater than or equal to 90 °.
  5. 5. A MOSFET device according to any of claims 1 to 4, characterized in that the gate blocks in the MOSFET device are axisymmetrically distributed or centrosymmetrically distributed.
  6. 6. The MOSFET device of any one of claims 1-4, wherein said gate is a T-gate, one end of said first strip-shaped sub-gate facing away from said second strip-shaped sub-gate extends beyond said active area, both ends of said second strip-shaped sub-gate extending beyond said active area; Or the MOSFET device is provided with two second strip-shaped sub-grids, the grid is an H-shaped grid, the first strip-shaped sub-grid is positioned in the active area, and two ends of the second strip-shaped sub-grid extend out of the active area.
  7. 7. A MOSFET device according to any one of claims 1 to 4, characterized in that the area of the gate block is 10nm 2 -40000nm 2 .
  8. 8. The MOSFET device of claim 7, wherein the second stripe-shaped sub-gate extends along a second direction, the gate block has a largest dimension in the second direction of 2nm-200nm, and/or the first stripe-shaped sub-gate extends along a first direction, the gate block has a largest dimension in the first direction of 5nm-200nm.
  9. 9. The MOSFET device of any one of claims 1-4, wherein the semiconductor substrate comprises a bottom semiconductor layer, a buried oxide layer, and a top semiconductor layer disposed in sequence, the top semiconductor layer comprising the active region, the gate electrode being located on a side of the top semiconductor layer facing away from the buried oxide layer.
  10. 10. A MOSFET device according to any one of claims 1 to 4, further comprising: The gate dielectric layer is positioned between the semiconductor substrate and the grid electrode; the insulating side wall is positioned on the surface of the side part of the grid electrode; The metal electrode comprises a gate electrode, a source electrode, a drain electrode and a body contact metal layer, the gate electrode is positioned on the surface of one side of the gate, which is away from the semiconductor substrate, the source electrode covers at least part of the area of the source region, the drain electrode covers at least part of the area of the drain region, the active region further comprises a body contact region, the body contact region is positioned on the side of the second strip-shaped sub-gate, which is away from the source region and the drain region, and the body contact metal layer covers at least part of the area of the body contact region; and shallow trenches surrounding the active region.

Description

MOSFET device Technical Field The invention relates to the technical field of transistors, in particular to a MOSFET device. Background Silicon-on-insulator (SOI) structures have advantages over bulk silicon substrates (bulksubstrate), such as elimination of latch-up, reduced short channel effects of the device, improved resistance to irradiation, and the like. Therefore, SOI substrates are currently used to fabricate MOSFET devices. While SOI technology brings about improved device and circuit performance as well as adverse effects, the biggest problem is that the floating body effect (floatingbodyeffect) of the SOI device is partially depleted, and the floating body effect causes the phenomena of the kek (king) effect, the drop of the drain breakdown voltage, the abnormal subthreshold slope and the like, thereby influencing the device performance. To address the floating body effect of SOI devices, bulk extraction is typically used to release accumulated holes. The traditional body extraction mode is to make the active region above the buried oxide layer in an electric floating state contact with the outside by using a T-shaped grid or an H-shaped grid so as to avoid the accumulation of holes in the region. However, the presence of the T-gate or H-gate may result in non-uniform doping of the channel edge region, affecting the performance and stability of the device. Disclosure of Invention In view of this, the present invention provides a MOSFET device to improve the performance and stability of the device. The invention provides a MOSFET device which comprises a semiconductor substrate and a grid electrode, wherein the semiconductor substrate comprises an active region, the grid electrode is arranged on one side of the semiconductor substrate and comprises a first strip-shaped sub-grid, a second strip-shaped sub-grid and a grid block, one end of the first strip-shaped sub-grid is connected with the second strip-shaped sub-grid to form a corner, the grid block is arranged at least one corner and is arranged in the active region, the active region comprises a channel region, a source region and a drain region, the channel region is arranged below the first strip-shaped sub-grid and the grid block, and the source region and the drain region are respectively arranged on two sides of the channel region. In the MOSFET device, the grid block covers the upper part of the low doped region at the corner, the grid voltage can generate an additional electric field, the invasion of a drain electric field is favorably shielded, so that the threshold voltage of the device is stabilized, the grid block can regulate the carrier concentration of the region through the electric field, so that the threshold voltage distribution in the width direction of the whole channel is more uniform, the space fluctuation degree of the threshold voltage is reduced, the uniformity of the current density distribution is improved, the control of the current path at the edge of the channel can be enhanced by the grid block, the off-state leakage current can be reduced, the injection degree of hot carriers into the grid dielectric layer can be reduced by the improvement of the suppression of the drain threshold voltage rolling effect and the uniformity of the current density distribution, and the service life of the device is prolonged. That is, the arrangement of the gate block can offset the influence of the non-uniform doping of the channel edge region on the performance of the device to a certain extent, and the performance and stability of the device are improved. In some optional embodiments, the grid block includes an inclined plane bridging between the first strip-shaped sub-grid and the second strip-shaped sub-grid, and the inclined plane is any one of a concave cambered surface, a convex cambered surface or a flat surface. In some alternative embodiments, the grid block includes a curved surface bridging between the first and second strip-shaped sub-grids, the curved surface including a first connecting surface and a second connecting surface that are connected. In some alternative embodiments, the first connection surface and the second connection surface are flat surfaces, an included angle between the first connection surface and the extending direction of the second strip-shaped sub-grid is greater than or equal to 90 °, and an included angle between the second connection surface and the extending direction of the first strip-shaped sub-grid is greater than or equal to 90 °. In some alternative embodiments, the gate blocks in the MOSFET device are axisymmetrically distributed or centrosymmetrically distributed. In some optional embodiments, the gate is a T-shaped gate, one end of the first strip-shaped sub-gate facing away from the second strip-shaped sub-gate extends beyond the active region, and both ends of the second strip-shaped sub-gate extend beyond the active region, or the MOSFET device has two second strip-shaped sub-