CN-121985562-A - Semiconductor transistor, preparation method thereof, chip and electronic equipment

Abstract

The application provides a semiconductor transistor, a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the voltage withstand capability of a device and reduce breakdown risk. The semiconductor transistor comprises a substrate, a drift layer, a source electrode, a drain electrode, a first field plate and a second field plate, wherein the drift layer is arranged on the substrate and comprises a first surface far away from one side of the substrate, and a drift region, a source electrode contact region and a drain electrode contact region which are arranged on the first surface. The source electrode and the first field plate are arranged on one side of the drift layer far away from the substrate, the source electrode is contacted with the source electrode contact region, the first field plate is electrically connected with the source electrode, and the orthographic projection of the first field plate on the first surface is overlapped with the drift region. The drain electrode and the second field plate are arranged on one side of the drift layer far away from the substrate, the drain electrode is in contact with the drain electrode contact region, the second field plate is electrically connected with the drain electrode, and orthographic projection of the second field plate on the first surface is overlapped with the drift region. The semiconductor transistor is applied to a high-frequency and high-power chip.

Inventors

• ZHAO DONGYAN
• CHEN YANNING
• JIANG TIANHAO
• HAO XINGYU
• WU BO
• LIU FANG
• DENG YONGFENG

Assignees

• 北京智芯微电子科技有限公司

Dates

Publication Date

20260505

Application Date

20251219

Claims (15)

1. 1. A semiconductor transistor, which comprises a semiconductor substrate, characterized by comprising the following steps: A substrate; The drift layer comprises a first surface far away from one side of the substrate, and a drift region, a source contact region and a drain contact region which are arranged on the first surface; the source electrode is in contact with the source electrode contact region, and the drain electrode is in contact with the drain electrode contact region; an interlayer dielectric layer covering the source electrode, the drain electrode and the drift layer; The first field plate comprises a first connecting part and a plurality of first contact posts, wherein one part of the first connecting part is arranged on one side, far away from the substrate, of the interlayer dielectric layer, and the other part of the first connecting part penetrates through the interlayer dielectric layer to be electrically connected with the source electrode; the second field plate comprises a second connecting part and a plurality of second contact posts, one part of the second connecting part is arranged on one side, far away from the substrate, of the interlayer dielectric layer, the other part of the second connecting part penetrates through the interlayer dielectric layer to be electrically connected with the drain electrode, the drain electrode contact region and the drift region are provided with connecting lines on the first surface, the second contact posts are positioned in the interlayer dielectric layer, at least part of the boundary of orthographic projection of the second contact posts on the first surface is positioned on one side, far away from the drain electrode contact region, of the connecting lines, and the second contact posts are connected with the second connecting part and are not in contact with the drift region.
2. 2. The semiconductor transistor of claim 1, wherein the plurality of first contact pillars are in at least two rows, each row of first contact pillars being aligned in a first direction parallel to the first surface; the plurality of second contact beams are arranged in a row, and the row of second contact beams is arranged along the first direction; The source and the drain are arranged along a second direction parallel to the first surface, the first direction intersecting the second direction.
3. 3. The semiconductor transistor of claim 1 or 2, further comprising a plurality of third field plates located in the drift region, the drift region having a first doping type, the third field plates having a second doping type; the first contact posts are arranged in the interval areas of the third field plates, and/or the second contact posts are arranged in the interval areas of the third field plates.
4. 4. The semiconductor transistor of claim 1, further comprising an etch stop layer disposed between the drift layer and the interlayer dielectric layer; The first contact pillar comprises an end part close to one side of the substrate, and the end part of the first contact pillar extends from the interlayer dielectric layer into the etching stop layer and is not contacted with the drift region; the second contact pillar includes an end portion near one side of the substrate, and the end portion of the second contact pillar extends from the interlayer dielectric layer into the etching stop layer and is not in contact with the drift region.
5. 5. The semiconductor transistor of claim 1, further comprising a gate, a fourth field plate, and a gate insulating layer, wherein the drift region is located between the source contact region and the drain contact region, wherein the gate insulating layer is disposed on a side of the drift region away from the substrate, wherein the fourth field plate is disposed on a side of the gate insulating layer away from the substrate, and wherein the gate is disposed on a side of the fourth field plate away from the substrate; the drift layer further comprises a body region arranged on the first surface, the source electrode contact region is arranged in the body region, the gate insulation layer comprises a first end close to one side of the body region and a second end close to one side of the drain electrode contact region, and the height of the first end compared with the first surface is larger than that of the second end compared with that of the first surface.
6. 6. The semiconductor transistor according to claim 5, wherein a surface of the gate insulating layer on a side away from the substrate has a multi-step; the multi-step steps are sequentially increased in height compared to the first surface in a direction from the drain contact region toward the source contact region.
7. 7. The semiconductor transistor of claim 1, further comprising a plurality of third field plates located in the drift region, the drift region having a first doping type, the third field plates having a second doping type; the plurality of third field plates are distributed in an array along a direction parallel to the first surface.
8. 8. The semiconductor transistor of claim 7, wherein the third field plate is columnar, the third field plate including an end distal from the substrate, the end of the third field plate having a spacing from the first surface.
9. 9. The semiconductor transistor of claim 7, wherein the drift layer further comprises a body region and a bottom field plate, the body region being disposed on the first surface, the bottom field plate being located on a side of the body region proximate the substrate, and the bottom field plate being electrically connected to the body region; The bottom field plate is also positioned on one side of the third field plate, which is close to the substrate, and the third field plate is electrically connected with the bottom field plate.
10. 10. A method of manufacturing a semiconductor transistor, comprising: Forming a drift layer on a substrate, wherein the drift layer comprises a first surface far away from one side of the substrate, and a drift region, a source contact region and a drain contact region which are arranged on the first surface; forming an etching stop layer on one side of the drift layer away from the substrate; Forming a source electrode and a drain electrode on one side of the drift layer away from the substrate, wherein the source electrode is in contact with the source electrode contact region, and the drain electrode is in contact with the drain electrode contact region; forming an interlayer dielectric layer covering the source electrode, the drain electrode, the drift layer and the etching stop layer; Forming a first connecting hole, a plurality of first contact holes, a second connecting hole and a plurality of second contact holes, wherein the first connecting hole penetrates through the interlayer dielectric layer and exposes the source electrode, the first contact holes penetrate through the interlayer dielectric layer and extend into the etching stop layer, orthographic projections of the first contact holes on the first surface are positioned in the drift region, the second connecting hole penetrates through the interlayer dielectric layer and exposes the drain electrode, the second contact holes penetrate through the interlayer dielectric layer and extend into the etching stop layer, the drain electrode contact region and the drift region are provided with connecting lines on the first surface, and at least part of boundaries of orthographic projections of the second contact holes on the first surface are positioned on one side of the connecting lines, which is far away from the drain electrode contact region; The method comprises the steps of forming a first connecting portion, a plurality of first contact pillars, a second connecting portion and a plurality of second contact pillars, wherein one part of the first connecting portion is located on one side, far away from a substrate, of an interlayer dielectric layer, the other part of the first connecting portion is electrically connected with a source electrode in a first connecting hole, the first contact pillars are located in a first contact hole, the plurality of first contact pillars are connected with the first connecting portion, one part of the second connecting portion is located on one side, far away from the substrate, of the interlayer dielectric layer, the other part of the second connecting portion is electrically connected with a drain electrode in a second connecting hole, the second contact pillars are located in a second contact hole, and the plurality of second contact pillars are connected with the second connecting portion.
11. 11. The method of manufacturing of claim 10, wherein prior to forming the first field plate and the second field plate, the method of manufacturing further comprises: forming a plurality of third field plates in the drift region by adopting an ion implantation process, wherein the drift region has a first doping type, and the third field plates have a second doping type; the first contact posts are arranged in the interval areas of the third field plates, and/or the second contact posts are arranged in the interval areas of the third field plates.
12. 12. The method of claim 11, wherein the ion implantation process has an energy greater than 200KeV.
13. 13. The method of manufacturing of claim 10, wherein prior to forming the source and drain electrodes, the method of manufacturing further comprises: Sequentially forming a plurality of insulating layers on one side of the drift region far away from the substrate, wherein the plurality of insulating layers are stacked to form a gate insulating layer with a multi-level step, and the multi-level step is sequentially increased compared with the height of the first surface along the direction from the drain contact region to the source contact region; Forming a fourth field plate, wherein the fourth field plate is positioned on one side of the gate insulation layer away from the substrate; And forming a grid electrode, wherein the grid electrode is positioned on one side of the fourth field plate, which is far away from the substrate.
14. 14. A chip comprising the semiconductor transistor according to any one of claims 1 to 9.
15. 15. An electronic device comprising the chip of claim 14.

Description

Semiconductor transistor, preparation method thereof, chip and electronic equipment Technical Field The present application relates to the field of semiconductor technologies, and in particular, to a semiconductor transistor, a method for manufacturing the semiconductor transistor, a chip, and an electronic device. Background Lateral diffusion metal oxide semiconductor (Lateral Diffused Metal Oxide Semiconductor, LDMOS) transistors are increasingly requiring higher withstand voltage levels, based on which how to improve the withstand voltage capability of the device and reduce the risk of device breakdown is a problem to be solved in the field. Disclosure of Invention The application provides a semiconductor transistor, a preparation method thereof, a chip and electronic equipment, and aims to improve the voltage-resistant capability of a device and reduce the risk of breakdown of the device. In order to achieve the above object, the embodiments of the present application provide the following technical solutions: In one aspect, a semiconductor transistor is provided, the semiconductor transistor including a substrate, a drift layer, a source electrode, a drain electrode, an interlayer dielectric layer, a first field plate and a second field plate, the drift layer being disposed on the substrate, the drift layer including a first surface remote from a side of the substrate, and a drift region, a source contact region and a drain contact region disposed on the first surface. The source electrode and the drain electrode are arranged on one side of the drift layer, which is far away from the substrate, the source electrode is in contact with the source electrode contact region, and the drain electrode is in contact with the drain electrode contact region. An interlayer dielectric layer covers the source electrode, the drain electrode and the drift layer. The first field plate comprises a first connecting part and a plurality of first contact posts, wherein one part of the first connecting part is arranged on one side, far away from the substrate, of the interlayer dielectric layer, and the other part of the first connecting part penetrates through the interlayer dielectric layer and is electrically connected with the source electrode. The first contact pillars are located in the interlayer dielectric layer, and orthographic projections of the first contact pillars on the first surface are located in the drift region. The plurality of first contact pillars are connected to the first connection portion and are not in contact with the drift region. The second field plate comprises a second connecting part and a plurality of second contact posts, one part of the second connecting part is arranged on one side, far away from the substrate, of the interlayer dielectric layer, the other part of the second connecting part penetrates through the interlayer dielectric layer to be electrically connected with the drain electrode, the drain electrode contact region and the drift region are provided with connecting lines on the first surface, the second contact posts are positioned in the interlayer dielectric layer, at least part of the boundary of orthographic projection of the second contact posts on the first surface is positioned on one side, far away from the drain electrode contact region, of the connecting lines, and the second contact posts are connected with the second connecting part and are not in contact with the drift region. In the above embodiment of the present application, the semiconductor transistor includes a field plate for adjusting and controlling the electric field strength of the drift region, where the field plate adopts a segmented design, and includes a first field plate and a second field plate, where the first field plate is electrically connected to the source electrode, and the first field plate includes a plurality of first contact pillars located in the interlayer dielectric layer, where the plurality of first contact pillars are electrically connected to the source electrode through a first connection portion, and orthographic projections of the plurality of first contact pillars on the first surface are located in the drift region, where the plurality of first contact pillars can promote the electric field strength of more regions in the longer drift region when the device is in an off state, so as to facilitate promotion of the voltage-withstanding capability of the device. The second field plate is electrically connected with the drain electrode, and the second field plate comprises a second connecting part and a plurality of second contact posts positioned in the interlayer dielectric layer, and the second contact posts are electrically connected with the drain electrode through the second connecting part. The drain contact region and the drift region are provided with a connecting line on the first surface, at least part of the boundary of the orthographic projection of the second con