CN-121985563-A - Radiation-resistant transverse integrated power semiconductor device

CN121985563ACN 121985563 ACN121985563 ACN 121985563ACN-121985563-A

Abstract

The invention provides a radiation-resistant transverse integrated power semiconductor device which comprises a P-type substrate, an N-type epitaxial region, a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a first P-type doped region and a second P-type doped region, a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is arranged on the surface of an active region of the device, the second dielectric layer is arranged on the surface of a field region of the device, the active region is of a closed structure and covers and exceeds the first N-type doped region, and a polycrystalline grid is arranged on the surface of the first dielectric layer. The drift region of the transverse device is of a longitudinal structure, the surface of the drift region is free of a thick field oxide layer, and a large amount of charges are prevented from being generated by total dose radiation, so that the performance of the device is greatly reduced due to the influence of the total dose radiation effect, and the device has high total dose radiation resistance.

Inventors

LI YANFEI
PENG HONG
XIE RUBIN
HONG GENSHEN

Assignees

中国电子科技集团公司第五十八研究所

Dates

Publication Date: 20260505
Application Date: 20260209

Claims (10)

1. A radiation-resistant laterally integrated power semiconductor device, comprising: The semiconductor device comprises a P-type substrate (11), an N-type epitaxial region (12) and a first N-type doped region (21), wherein the N-type epitaxial region (12) is arranged on the surface of the P-type substrate (11), and the first N-type doped region (21) is arranged between the P-type substrate (11) and the N-type epitaxial region (12); The semiconductor device comprises a second N-type doped region (22), a third N-type doped region (23), a fourth N-type doped region (24), a first P-type doped region (31) and a second P-type doped region (32), wherein the second N-type doped region (22) and the first P-type doped region (31) are arranged in an N-type epitaxial region (12), the third N-type doped region (23) and the second P-type doped region (32) are arranged in a first P-type doped region (31), the third N-type doped region (23) and the second P-type doped region (32) are tangential and do not overlap, the fourth N-type doped region (24) is arranged in the second N-type doped region (22), and the second N-type doped region (22) is connected with the first N-type doped region (21); The first dielectric layer (61) and the second dielectric layer (62), the first dielectric layer (61) is arranged on the surface of an active region (40) of the device, the second dielectric layer (62) is arranged on the surface of a field region (41) of the device, and the active region (40) is of a closed structure and covers and exceeds the first N-type doped region (21); And the polycrystalline grid (51) is arranged on the surface of the first dielectric layer (61).
2. A radiation-resistant laterally integrated power semiconductor device as claimed in claim 1, characterized in that the third N-doped region (23) forms a source region of the device, the second P-doped region (32) forms a body region of the device, the fourth N-doped region (24) forms a drain region of the device, the channel of the device is of a longitudinal structure, and a current of the device flows from the third N-doped region (23) through the first P-doped region (31) and the N-epitaxial region (12) to the fourth N-doped region (24).
3. A radiation-resistant laterally integrated power semiconductor device according to claim 1, characterized in that the fourth N-doped region (24) and the second N-doped region (22) are stripe-shaped structures, non-closed ring-shaped structures or closed ring-shaped structures.
4. A radiation-resistant laterally integrated power semiconductor device as recited in claim 1, wherein, The implantation dosage of the first N-type doped region (21) and the second N-type doped region (22) is 5E14cm -2 ~1E16cm -2 .
5. A radiation-resistant laterally integrated power semiconductor device as claimed in claim 1, characterized in that the second P-type doped region (32) and the poly-gate (51) are located within the active region (40), and the first P-type doped region (31) and the second P-type doped region (32) are of a closed ring-shaped structure.
6. The radiation-resistant laterally integrated power semiconductor device as claimed in claim 1, wherein the poly-gate (51) has a stripe-shaped structure and at least one stripe-shaped structure, wherein the poly-gate (51) overlaps the third N-type doped region (23) and the second P-type doped region (32) respectively when in the stripe-shaped structure, and wherein the poly-gate (51) has a channel width direction exceeding the third N-type doped region (23) and not exceeding the second P-type doped region (32).
7. A radiation-resistant laterally integrated power semiconductor device according to claim 1, characterized in that the poly-gate (51) is a gate plate with a plurality of square-structured holes, hexagonal-structured holes or circular-structured holes arranged in an array.
8. A radiation-resistant laterally integrated power semiconductor device as claimed in claim 7, characterized in that, when the polycrystalline gate (51) is an array square structure hole, the first P-type doped region (31) is of two concentric closed annular structures, one second P-type doped region (32) and one third N-type doped region (23) are arranged in the first P-type doped region (31) at the outer side in a tangential manner, or only one second P-type doped region (32) is arranged, one second P-type doped region (32) of a square structure is arranged in the first P-type doped region (31) at the inner side, and the third N-type doped region (23) of a closed annular structure is arranged in the second P-type doped region (32) at the outer side in a tangential manner.
9. A radiation-resistant laterally integrated power semiconductor device as claimed in claim 7, characterized in that, when the polycrystalline gate (51) is an array of holes of hexagonal structure, the first P-type doped region (31) is of two concentric closed annular structures, one second P-type doped region (32) and one third N-type doped region (23) are arranged in the first P-type doped region (31) on the outer side and tangential, or only one second P-type doped region (32) is arranged, one second P-type doped region (32) of hexagonal structure is arranged in the first P-type doped region (31) on the inner side, and one third N-type doped region (23) of closed annular structure is tangential to the outer side of the second P-type doped region (32) of hexagonal structure.
10. A radiation-resistant laterally integrated power semiconductor device as claimed in claim 7, characterized in that, when the polycrystalline gate (51) is an array of circular structure holes, the first P-type doped region (31) is of two concentric closed annular structures, one second P-type doped region (32) and one third N-type doped region (23) are arranged in the first P-type doped region (31) on the outer side and tangential, or only one second P-type doped region (32) is arranged, one second P-type doped region (32) of a circular structure is arranged in the first P-type doped region (31) on the inner side, and the third N-type doped region (23) of a closed annular structure is tangential to the outer side of the second P-type doped region (32) of the circular structure.

Description

Radiation-resistant transverse integrated power semiconductor device Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to a radiation-resistant transverse integrated power semiconductor device. Background The high-voltage transverse double-diffusion MOSFET device is used as a key device and plays an important role in power management chips of space electronic systems such as space vehicles, satellites and the like, and the high-voltage transverse device is very sensitive to the effect of ionizing radiation. The charge generated by the ionizing radiation may cause stable defects in the dielectric materials used in the fabrication process that may lead to device threshold voltage drift, strong leakage currents, and parasitic conductive path formation. Particularly for high-voltage lateral devices, as the operating voltage increases, the radiation effect of the devices is greatly affected, and the radiation resistance of the high-voltage devices limits the application of the high-voltage devices in space radiation environments. In order for the chip to work properly in a severe irradiation environment, the high voltage device must be radiation-resistant reinforced. Therefore, the invention provides the radiation-resistant transverse integrated power semiconductor device, which can avoid field electric leakage and device performance degradation under the total dose radiation environment, and improve the total dose radiation resistance of the device. Disclosure of Invention The invention aims to provide a radiation-resistant transverse integrated power semiconductor device, which is used for solving the problems of radiation leakage and characteristic degradation of a high-voltage device in the radiation-resistant high-voltage process. In order to solve the technical problems, the invention provides a radiation-resistant transverse integrated power semiconductor device, which comprises: The semiconductor device comprises a P-type substrate, an N-type epitaxial region and a first N-type doped region, wherein the N-type epitaxial region is arranged on the surface of the P-type substrate, and the first N-type doped region is positioned between the P-type substrate and the N-type epitaxial region; The epitaxial device comprises a first N-type doped region, a second N-type doped region, a third N-type doped region, a fourth N-type doped region, a first P-type doped region and a second P-type doped region, wherein the second N-type doped region and the first P-type doped region are arranged in an N-type epitaxial region, the third N-type doped region and the second P-type doped region are arranged in a first P-type doped region, the third N-type doped region and the second P-type doped region are tangential and do not overlap, the fourth N-type doped region is arranged in the second N-type doped region, and the second N-type doped region is connected with the first N-type doped region; The first dielectric layer is arranged on the surface of the active area of the device, the second dielectric layer is arranged on the surface of the field area of the device, and the active area is of a closed structure and covers and exceeds the first N-type doped area; and the polycrystalline grid is arranged on the surface of the first dielectric layer. Preferably, the third N-type doped region forms a source region of the device, the second P-type doped region forms a body region of the device, the fourth N-type doped region forms a drain region of the device, a channel of the device is of a longitudinal structure, and current of the device flows from the third N-type doped region to the fourth N-type doped region through the first P-type doped region and the N-type epitaxial region. Preferably, the fourth N-type doped region and the second N-type doped region are in a stripe structure, a non-closed loop structure or a closed loop structure. Preferably, the implantation dose of the first N-type doped region and the second N-type doped region is 5E14cm -2~1E16cm-2. Preferably, the second P-type doped region and the polycrystalline gate are located in the active region, and the first P-type doped region and the second P-type doped region are in a closed annular structure. Preferably, the polycrystalline gate has a strip structure, and the strip structure is at least one strip, and when the polycrystalline gate has the strip structure, the polycrystalline gate is overlapped with the third N-type doped region and the second P-type doped region respectively, and the channel width direction of the polycrystalline gate exceeds the third N-type doped region and does not exceed the second P-type doped region. Preferably, the polycrystalline grid is a grid plate with a plurality of square structure holes, hexagonal structure holes or circular structure holes in an array. Preferably, when the polycrystalline grid is an array square structure hole, the first P-type doped region is of two c