CN-121985564-A - Shielded gate trench transistor, manufacturing method thereof and layout

CN121985564ACN 121985564 ACN121985564 ACN 121985564ACN-121985564-A

Abstract

The invention provides a shielded gate trench transistor, a method of manufacturing the same, and a layout thereof, wherein a control gate structure is formed in a first trench, a shielded gate structure is formed in a second trench, the first trenches surround the corresponding second trenches, the first trenches are regular hexagons in the extending direction of the semiconductor substrate and the second trenches are located at the centers of the first trenches. That is, a regular hexagonal control gate structure is formed, the cell channel density is increased, and the specific on-resistance (Rsp) is reduced. Meanwhile, the shielding gate structure is positioned at the center of the control gate structure, three-dimensional (3D) depletion is formed, the specific on-resistance is further effectively reduced, and the performance of the shielding gate trench transistor is improved. Further, the distances between the shielding grid structures are consistent, and accordingly, charge balance is completely matched, so that the breakdown stability of the shielding grid trench transistor is improved.

Inventors

XIAO XUAN
LI DAN
TAN JUNTING
YE JUN
YANG ZHIYU

Assignees

无锡华润华晶微电子有限公司

Dates

Publication Date: 20260505
Application Date: 20241031

Claims (10)

1. A shielded gate trench transistor, the shielded gate trench transistor comprising: A semiconductor substrate in which a plurality of first trenches and a plurality of second trenches are formed, each of the first trenches surrounding a corresponding second trench, the second trench being located at a center of the first trench in an extending direction of the semiconductor substrate, and the first trench being in a regular hexagon shape; a control gate structure in the first trench, and And a shielding gate structure positioned in the second groove.
2. The shielded gate trench transistor of claim 1 wherein the second trench is deeper than the first trench.
3. The shielded gate trench transistor of claim 1 wherein the second trench is cylindrical or regular hexagonal.
4. A shielded gate trench type transistor according to any one of claims 1 to 3, wherein adjacent ones of the first trenches are connected in an extending direction of the semiconductor substrate.
5. The shielded gate trench transistor of any one of claims 1-3 wherein the control gate structure comprises a control gate dielectric layer in the first trench and a control gate electrode on the control gate dielectric layer, and wherein the shielded gate structure comprises a shielded gate dielectric layer in the second trench and a shielded gate electrode on the shielded gate dielectric layer.
6. The shielded gate trench transistor of claim 5, the method is characterized in that the shielded gate trench transistor further comprises: A well region in the semiconductor substrate, the well region being in the semiconductor substrate between the first trench and the second trench; a source region in the well region, and The contact structure comprises a first contact structure and a second contact structure connected with the first contact structure, the first contact structure is electrically connected with the source region, the second contact structure is electrically connected with the shielding gate electrode, and the first contact structure surrounds the second groove and is connected with the shielding gate dielectric layer.
7. The shielded gate trench transistor of claim 6 wherein the first contact structure is circular or regular hexagonal and the second contact structure is stripe-shaped in the direction of extension of the semiconductor substrate.
8. A method for manufacturing a shielded gate trench transistor is characterized in that, the manufacturing method of the shielded gate trench transistor comprises the following steps: providing a semiconductor substrate; Etching the semiconductor substrate to form a plurality of first trenches and a plurality of second trenches in the semiconductor substrate, each of the first trenches surrounding a corresponding one of the second trenches, the second trench being located at a center of the first trench and the first trench being in a regular hexagon shape in an extending direction of the semiconductor substrate, and And forming a control gate structure in the first groove and forming a shielding gate structure in the second groove.
9. The method of manufacturing a shielded gate trench transistor as recited in claim 8, the manufacturing method of the shielded gate trench transistor is characterized by further comprising the following steps: performing a first ion implantation process on the semiconductor substrate to form a first ion implantation region in the semiconductor substrate, and Performing a second ion implantation process on the first ion implantation region to form a second ion implantation region in the first ion implantation region; the first trench and the second trench penetrate through the first ion implantation region and the second ion implantation region, so that the first ion implantation region is divided into a plurality of well regions, and the second ion implantation region is divided into a plurality of source regions.
10. A shielded gate trench transistor layout, the shielded gate trench transistor layout comprising: A first pattern layer including a plurality of first patterns, the first patterns being regular hexagons, and And a second layer comprising a plurality of second patterns, the second patterns being located within the first patterns.

Description

Shielded gate trench transistor, manufacturing method thereof and layout Technical Field The invention relates to the technical field of semiconductor manufacturing, in particular to a shielded gate trench transistor, a manufacturing method and a layout thereof. Background The shielded gate trench type (SHIELD GATE TRENCH, SGT) transistor has the advantages of low specific on-resistance, low miller capacitance, low power loss, small parasitic capacitance, high switching speed, good high-frequency characteristic and the like, and occupies a larger market share in the middle-low voltage application field below 250V. However, the performance of the existing shielded gate trench transistor cannot meet the needs of people, and how to further improve the performance of the shielded gate trench transistor is a long pursuit of those skilled in the art. Disclosure of Invention The invention aims to provide a shielded gate trench transistor, a manufacturing method and a layout thereof, so as to improve the performance of the shielded gate trench transistor. Accordingly, the present invention provides a shielded gate trench transistor comprising: A semiconductor substrate in which a plurality of first trenches and a plurality of second trenches are formed, each of the first trenches surrounding a corresponding second trench, the second trench being located at a center of the first trench in an extending direction of the semiconductor substrate, and the first trench being in a regular hexagon shape; a control gate structure in the first trench, and And a shielding gate structure positioned in the second groove. Optionally, in the shielded gate trench transistor, the second trench is deeper than the first trench. Optionally, in the shielded gate trench transistor, the second trench is cylindrical or regular hexagonal prism. Optionally, in the shielded gate trench transistor, adjacent first trenches are connected in an extending direction of the semiconductor substrate. Optionally, in the shielded gate trench transistor, the control gate structure includes a control gate dielectric layer located in the first trench and a control gate electrode located on the control gate dielectric layer, and the shielded gate structure includes a shielded gate dielectric layer located in the second trench and a shielded gate electrode located on the shielded gate dielectric layer. Optionally, in the shielded gate trench transistor, the shielded gate trench transistor further includes: A well region in the semiconductor substrate, the well region being in the semiconductor substrate between the first trench and the second trench; a source region in the well region, and The contact structure comprises a first contact structure and a second contact structure connected with the first contact structure, the first contact structure is electrically connected with the source region, the second contact structure is electrically connected with the shielding gate electrode, and the first contact structure surrounds the second groove and is connected with the shielding gate dielectric layer. Optionally, in the shielded gate trench transistor, in an extending direction of the semiconductor substrate, the first contact structure is circular or regular hexagonal, and the second contact structure is stripe-shaped. The invention also provides a manufacturing method of the shielded gate trench transistor, which comprises the following steps: providing a semiconductor substrate; Etching the semiconductor substrate to form a plurality of first trenches and a plurality of second trenches in the semiconductor substrate, each of the first trenches surrounding a corresponding one of the second trenches, the second trench being located at a center of the first trench and the first trench being in a regular hexagon shape in an extending direction of the semiconductor substrate, and And forming a control gate structure in the first groove and forming a shielding gate structure in the second groove. Optionally, in the method for manufacturing a shielded gate trench transistor, the method for manufacturing a shielded gate trench transistor further includes: performing a first ion implantation process on the semiconductor substrate to form a first ion implantation region in the semiconductor substrate, and Performing a second ion implantation process on the first ion implantation region to form a second ion implantation region in the first ion implantation region; the first trench and the second trench penetrate through the first ion implantation region and the second ion implantation region, so that the first ion implantation region is divided into a plurality of well regions, and the second ion implantation region is divided into a plurality of source regions. The invention also provides a shield gate trench transistor layout, which comprises: A first pattern layer including a plurality of first patterns, the first patterns being regular hexagons, and And a second