Search

CN-121985566-A - Double-gate two-dimensional transistor for multifunctional storage and logic calculation

CN121985566ACN 121985566 ACN121985566 ACN 121985566ACN-121985566-A

Abstract

The invention relates to the technical field of semiconductors and discloses a double-gate two-dimensional transistor for multifunctional storage and logic calculation, which comprises a substrate, a floating gate layer, a tunneling layer, a channel layer, a top gate insulating layer, a bottom gate electrode, a top gate electrode, a source electrode and a drain electrode, wherein the substrate is an N-type single-polishing silicon oxide wafer, the floating gate layer is a graphene layer, the tunneling layer is a hexagonal boron nitride layer, the channel layer is a molybdenum disulfide layer, the top gate insulating layer is a hexagonal boron nitride layer, the floating gate layer is arranged on the upper surface of the substrate, the tunneling layer covers the upper surface of the floating gate layer, the channel layer is arranged on the upper surface of the tunneling layer, and the top gate insulating layer covers the upper surface of the channel layer. By means of the heterogeneous stacking structure of the h-BN/MoS graphene and the double-gate independent regulation and control mechanism, single-device integrated integration of light perception, nonvolatile storage and logic operation is achieved, extra splicing links of sensing, storage and calculation units in a traditional system are omitted, and a hardware architecture is greatly simplified.

Inventors

  • TIAN JUNLONG
  • YANG ZAIWEI
  • ZHANG YIHAO
  • CHEN CAN

Assignees

  • 贵州大学

Dates

Publication Date
20260505
Application Date
20260123

Claims (10)

  1. 1. The double-gate two-dimensional transistor for multifunctional storage and logic calculation is characterized by comprising a substrate, a floating gate layer, a tunneling layer, a channel layer, a top gate insulating layer, a bottom gate electrode, a top gate electrode, a source electrode and a drain electrode, wherein the substrate is an N-type single-polishing silicon oxide wafer, the floating gate layer is a graphene layer, the tunneling layer is a hexagonal boron nitride layer, the channel layer is a molybdenum disulfide layer, the top gate insulating layer is a hexagonal boron nitride layer, the floating gate layer is arranged on the upper surface of the substrate, the tunneling layer covers the upper surface of the floating gate layer, the channel layer is arranged on the upper surface of the tunneling layer, the top gate insulating layer covers the upper surface of the channel layer, the bottom gate electrode is electrically connected with the substrate, the top gate electrode is arranged on the upper surface of the top gate insulating layer, the source electrode and the drain electrode are respectively arranged at two ends of the channel layer and are electrically connected with the channel layer, the source electrode and the drain electrode are of a Cr/Au composite structure, the thickness of the Cr layer is 5nm, and the thickness of the Au layer is 50nm.
  2. 2. The dual-gate two-dimensional transistor for multifunctional storage and logic computation according to claim 1, wherein the thickness of the SiO 2 layer in the substrate is 285nm, the graphene layer is of a multilayer structure, the G peak is 1580cm -1 and the 2D peak is 2717cm -1 in a Raman spectrum of the graphene layer, the E 2g characteristic peak is 1366cm -1 in the Raman spectrum of the hexagonal boron nitride layer, and the E 2g peak is 383cm -1 ,A 1g peak 407cm -1 in the Raman spectrum of the molybdenum disulfide layer.
  3. 3. The dual-gate two-dimensional transistor for multifunctional storage and logic computation according to claim 1, wherein the heterostructure of the dual-gate two-dimensional transistor is a stacked structure of a substrate, a floating gate layer, a tunneling layer, a channel layer and a top gate insulating layer in sequence, h-BN/MoS 2 /h-BN/graphene is formed, the electron affinity of the tunneling layer is 1.9-2.3eV, the band gap is 5.96eV, the electron affinity of the channel layer is 4.0eV, the band gap is 1.24eV, the work function of the floating gate layer is 4.6eV, and the work functions of Cr layers in a source electrode and a drain electrode are 4.5eV.
  4. 4. A non-volatile memory implementation method based on the double-gate two-dimensional transistor according to any one of claims 1-3 is characterized by comprising a programming step and an erasing step, wherein the programming step is to apply a voltage pulse with +40V and a pulse width of 1s to a bottom gate electrode, electrons in a channel layer tunnel to a floating gate layer through a tunneling layer and are captured, so that the device is in a high resistance state, the erasing step is to apply a voltage pulse with-40V and a pulse width of 1s to the bottom gate electrode, and electrons captured in the floating gate layer are released to the channel layer, so that the device is in a low resistance state.
  5. 5. The method of claim 4, wherein the memory window of the double-gate two-dimensional transistor increases linearly with the maximum value of the bottom gate voltage, the ratio of the range of the memory window to the range of the sweep voltage reaches 83.5% when the maximum value of the bottom gate voltage is 50V, the data retention time of the device exceeds 100s in the programming state, the current does not decay significantly, and the erase/program ratio decreases by no more than 10% after 100 program-erase cycles.
  6. 6. A method for realizing light perception based on the double-gate two-dimensional transistor according to any one of claims 1-3, characterized in that the channel layer generates hole-electron pairs under light irradiation to increase channel carrier concentration, the wavelength of the light comprises 365nm, 530nm and 625nm, the channel current increases with the decrease of the wavelength of the irradiated light under the same gate voltage condition, and the channel current is minimum under the dark condition.
  7. 7. A logic OR gate implementation method based on the double-gate two-dimensional transistor is characterized in that bottom gate voltage and top gate voltage are used as input signals, source leakage current is used as output signals, the input logic 1 is defined when the bottom gate voltage is 40V, the input logic 0 is defined when the bottom gate voltage is 40V, the input logic 1 is defined when the top gate voltage is 5V, the input logic 0 is defined when the top gate voltage is 5V, the source leakage current is about 10 -12 A when the input combination is 40V and 5V, the output logic 0 is output, and the source leakage current is obviously greater than 10 -12 A and the output logic 1 is output under the rest of input combinations.
  8. 8. A logic NOT gate implementation method based on the double-gate two-dimensional transistor is characterized in that bottom gate voltage is used as an input signal and source leakage current is used as an output signal, wherein the input logic '1' is defined when the bottom gate voltage is-40V, electrons are released from a floating gate layer to a channel layer at the moment, channel carrier concentration is increased, the source leakage current is increased, the output logic '1' is output, the input logic '0' is defined when the bottom gate voltage is 40V, electrons are captured by the floating gate layer at the moment, the channel carrier concentration is reduced, the source leakage current is reduced, and the output logic '0' is output.
  9. 9. A logic AND gate implementation method based on the double-gate two-dimensional transistor is characterized by comprising two double-gate two-dimensional transistors with the same structure, namely M1 AND M2, wherein the M1 AND the M2 are respectively marked as M1 AND M2, the drain electrode of the M1 is electrically connected with the source electrode of the M2, the top gate electrodes of the two transistors are applied with 5V voltage to enhance the conduction sensitivity, the bottom gate voltage V bg1 of the M1 AND the bottom gate voltage V bg2 of the M2 are used as input signals, the total source leakage current of a series circuit is used as output signals, the M1 AND the M2 are simultaneously conducted only when V bg1 AND V bg2 are both-40V (input logic '1'), the total source leakage current is obviously increased, when any input is 40V (input logic '0'), the corresponding transistor is cut off, the total source leakage current is close to 0, AND the logic '0' is output.
  10. 10. A nonvolatile SR trigger based on a dual-gate two-dimensional transistor is characterized by comprising two dual-gate two-dimensional transistors with the same structure, namely M1 and M2, wherein a drain electrode of M1 is electrically connected with a gate of M2, a drain electrode of M2 is electrically connected with a gate of M1 to form a cross coupling structure, bottom gate electrodes of the two transistors are used for nonvolatile state storage, a top gate electrode is respectively connected with a set signal S and a reset signal R, when S is an effective signal, M1 is turned on and M2 is turned off, the trigger outputs logic '1', when R is an effective signal, M2 is turned on and M1 is turned off, the trigger outputs logic '0', and when no effective signal is available, the trigger keeps the current output state to realize nonvolatile storage.

Description

Double-gate two-dimensional transistor for multifunctional storage and logic calculation Technical Field The invention relates to the technical field of semiconductors, in particular to a double-gate two-dimensional transistor for multifunctional storage and logic calculation. Background With the rapid development of emerging technologies such as artificial intelligence, internet of things and big data, the demands for global information storage and calculation are exponentially increased, and unprecedented stringent requirements on the integration level, power consumption and versatility of electronic devices are put forward. The traditional silicon-based transistor is used as a core hardware foundation of the electronic information industry, is subjected to size miniaturization for decades under the drive of moore's law, but is approaching to the restriction of physical limit and quantum tunneling effect at present, and faces the bottlenecks that the integration level is difficult to further improve, the leakage loss is aggravated, the power consumption is high, and the like. Under the background, the 'integrated memory and calculation' architecture with the memory and calculation functions becomes the core direction for breaking through the technical bottleneck, and the data memory and logic calculation functions are deeply fused at the device level, so that the migration loss of data between the memory unit and the calculation unit can be greatly reduced, the energy efficiency and the response speed of the system are remarkably improved, and the architecture becomes a key technical path for constructing the next-generation low-power-consumption high-density information processing system. The two-dimensional material provides an ideal material platform for the research and development of a memory integrated device by virtue of an atomically flat surface, an adjustable energy band structure, excellent carrier transport characteristics and good compatibility with heterogeneous materials. Compared with the traditional silicon-based material, the atomic-level thickness of the two-dimensional material can effectively inhibit short channel effect, and the flexible energy band regulation and control capability can realize accurate modulation of carrier concentration and transport characteristics, so that the two-dimensional material is widely applied to the design of novel storage, logic operation and other multifunctional devices. At present, transistor devices based on two-dimensional materials have become research hotspots in academia and industry, and related researches mainly surround single-function optimization or preliminary multi-function integration expansion, so as to attempt to break through the limitation of the traditional technology through innovation of material characteristics and device structures. In terms of memory function, the existing two-dimensional material memory device mainly comprises a floating gate memory, a resistive random access memory, a ferroelectric memory and the like. The floating gate type memory device realizes nonvolatile memory of data through capturing and releasing charges on the floating gate layer, and has the advantages of simple programming/erasing operation, good data retention and the like. In recent years, researchers have developed floating gate memories based on two-dimensional materials such as ReS 2、MoTe2 and the like, and realized multi-bit memory expansion by constructing a two-dimensional heterostructure, but the floating gate memories have obvious defects that on one hand, the devices adopt a single gate regulation mode, only limited charge trapping efficiency regulation can be realized, so that a memory window is narrow and the data holding capacity is insufficient, and on the other hand, the device design takes a pure memory function as a core, lacks a collaborative compatible design with a logic operation function and cannot meet the requirement of a memory-calculation integrated system on multi-functional integration. In the aspect of logic operation, the existing two-dimensional material logic device mainly realizes basic Boolean operation through the on/off state of a regulating device, but is limited by the regulating capability of a single grid electrode, the logic state switching speed is low, the function is single, the dynamic regulating requirement of a complex logic circuit is difficult to support, the logic operation process is required to rely on continuous power supply to maintain the state, and the power consumption is high. The advent of dual gate modulation technology provides a new solution for the multifunctional integration of two-dimensional material devices. The technology can regulate and control the carrier concentration, the energy band structure and the tunneling barrier height of the two-dimensional channel simultaneously through independent or cooperative modulation of the top grid electrode and the bottom grid electrode, a