Search

CN-121985567-A - Semiconductor device and preparation method thereof

CN121985567ACN 121985567 ACN121985567 ACN 121985567ACN-121985567-A

Abstract

The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof, wherein the semiconductor device comprises a substrate; the device comprises a substrate, a substrate isolation layer embedded in the substrate and with one side surface exposed on the surface of the substrate, a device substrate layer covering the exposed surface of the substrate isolation layer and comprising at least two substrate sub-layers stacked on the surface of the substrate, an isolation well region layer, an isolation ring and a device region, wherein the isolation well region layer is arranged in the substrate sub-layers, two ends of the isolation well region layer penetrate through the substrate sub-layers, the isolation well region layer in the substrate sub-layers adjacent to the surface of the substrate extends to the substrate isolation layer, the isolation well region layers are connected with the substrate isolation layer to form an isolation ring, and the device region is arranged in an isolation region surrounded by the isolation ring in the device substrate layer and is isolated by the isolation ring. The application can ensure the isolation effect of the isolation ring and improve the stability of the device.

Inventors

  • CUI JIA
  • LI QINGHUA
  • Xu luan

Assignees

  • 中芯国际集成电路制造（天津）有限公司
  • 中芯国际集成电路制造(上海)有限公司

Dates

Publication Date
20260505
Application Date
20241029

Claims (11)

  1. 1. A semiconductor device, the semiconductor device comprising: A substrate (100); a substrate isolation layer (110) embedded in the substrate (100) and having one side surface exposed to the surface of the substrate (100); A device substrate layer (200) covering an exposed surface of the base isolation layer (110), comprising at least two substrate sub-layers (210) stacked on a surface of the base (100); The isolation well region layers (220) are positioned in the substrate sub-layers (210), two ends of each isolation well region layer penetrate through the substrate sub-layers (210), the isolation well region layers (220) of the adjacent substrate sub-layers (210) are connected, the isolation well region layers (220) in the substrate sub-layers (210) adjacent to the surface of the substrate (100) extend to the substrate isolation layers (110), and the isolation well region layers (220) in the substrate sub-layers (210) are connected with the substrate isolation layers (110) to form isolation rings; And the device region (300) is positioned in the isolation region surrounded by the isolation ring in the device substrate layer (200) and is isolated by the isolation ring.
  2. 2. The semiconductor device according to claim 1, wherein the isolation well region layer (220) adjacent to the base isolation layer (110) is bonded to the base isolation layer (110), and wherein the two adjacent isolation well region layers (220) are bonded.
  3. 3. The semiconductor device according to claim 1, wherein the at least two substrate sub-layers (210) are grown stepwise, and the isolation well region layer (220) is formed by ion implantation of the current substrate sub-layer (210) after formation of the current substrate sub-layer (210) and before growth of the next substrate sub-layer (210).
  4. 4. The semiconductor device according to claim 1, wherein the isolation well region layer (220) adjoining the base isolation layer (110) diffuses into the base isolation layer (110), and wherein of the adjoining two isolation well region layers (220), the later-formed isolation well region layer (220) diffuses into the earlier-formed isolation well region layer (220).
  5. 5. The semiconductor device according to claim 1, wherein the base (100) and the device substrate layer (200) are of the same conductivity type and the spacer ring and the device substrate layer (200) are of different conductivity type.
  6. 6. The semiconductor device according to any one of claims 1 to 5, wherein the thickness of the substrate sub-layer (210) is equal to or less than a predetermined thickness, the predetermined thickness being 3.5 μm to 4 μm.
  7. 7. The semiconductor device according to any of claims 1-5, characterized in that the longitudinal spacing between the device region (300) and the spacer ring is 0.1-2.3 μm.
  8. 8. The semiconductor device according to any of claims 1-5, wherein a lateral spacing between the device region (300) and the spacer ring is 0.1-2.5um.
  9. 9. A method of manufacturing a semiconductor device, the method comprising: Providing a substrate (100); Forming a substrate isolation layer (110) in the substrate (100) with one side surface exposed to the surface of the substrate (100); Forming at least two substrate sub-layers (210) arranged in a stacked manner on the surface of the base (100) to obtain a device substrate layer (200) covering the exposed surface of the base isolation layer (110); After each substrate sub-layer (210) is formed, forming an isolation well region layer (220) with two ends penetrating through the substrate sub-layers (210) in the substrate sub-layers (210), obtaining an isolation well region layer (220), connecting the isolation well region layers (220) of adjacent substrate sub-layers (210), extending the isolation well region layer (220) in the substrate sub-layers (210) adjacent to the surface of the substrate (100) to the substrate isolation layer (110), and connecting the isolation well region layer (220) in each substrate sub-layer (210) and the substrate isolation layer (110) to form an isolation ring; And forming a device region (300) in the device substrate layer (200) in an isolation region surrounded by the isolation ring, wherein the isolation ring isolates the device region (300).
  10. 10. The method according to claim 9, wherein the at least two substrate sub-layers (210) are grown in steps, and the isolation well region layer (220) is formed by ion implantation of the current substrate sub-layer (210) after the formation of the current substrate sub-layer (210) and before the growth of the next substrate sub-layer (210); The energy of the ion implantation is 100-1000keV, and the dosage of the ion implantation is 10 12 -10 16 /cm 2 .
  11. 11. The method of claim 9, wherein the at least two substrate sub-layers (210) comprise a first substrate sub-layer (211) and a second substrate sub-layer (212), each of the isolation well region layers (220) comprises a first isolation well region layer (221) and a second isolation well region layer (222), and the forming of the at least two epitaxial substrates and the isolation well region layer (220) comprises: Forming the first substrate sub-layer (211) on the surface of the base (100), wherein the first substrate sub-layer (211) covers the exposed surface of the base isolation layer (110); forming the first isolation well region layer (221) in the first substrate sub-layer (211) through ion implantation, wherein two ends of the first isolation well region layer (221) penetrate through the first substrate sub-layer (211) and one end of the first isolation well region layer is attached to the substrate isolation layer (110); Forming the second substrate sub-layer (212) on one side of the first substrate sub-layer (211) facing away from the surface of the base (100); And forming a second isolation well region layer (222) which is laminated on the first isolation well region layer (221) in the second substrate sub-layer (212) through ion implantation, wherein two ends of the second isolation well region layer (222) penetrate through the second substrate sub-layer (212) and one end of the second isolation well region layer is attached to the first isolation well region layer (221).

Description

Semiconductor device and preparation method thereof Technical Field The application relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof. Background In the middle/high voltage device manufacturing process, isolation between different devices is a very critical structure, and taking LDMOS (Lateral Diffused Metal Oxide Semiconductor, laterally diffused metal oxide semiconductor) as an example, the isolation structure can effectively isolate the devices from the P-type substrate, so as to prevent the problem of electric leakage between the devices. In the prior art, an ion implantation doping method is generally adopted to form an isolation layer and an isolation well region. However, due to insufficient ion implantation capability of the isolation well region in the actual process, deep implantation cannot be realized, so that the concentration of the isolation well region reaching the bottom through annealing diffusion is small, even the situation that the isolation well region cannot be connected with the isolation layer occurs, and electric leakage between a device and a P-type substrate can be directly caused in the actual use process. Disclosure of Invention In order to solve the above problems in the prior art, the present application provides a semiconductor device and a method for manufacturing the same, and the specific technical scheme is as follows: In one aspect, the present application provides a semiconductor device comprising a substrate and at least one transistor structure, the transistor structure comprising: A substrate; the substrate isolation layer is embedded in the substrate, and one side surface of the substrate isolation layer is exposed on the surface of the substrate; the device substrate layer covers the exposed surface of the base isolation layer and comprises at least two substrate sub-layers which are laminated on the surface of the base; the isolation well region layers are positioned in the substrate sub-layers, two ends of the isolation well region layers penetrate through the substrate sub-layers, the isolation well region layers in the substrate sub-layers adjacent to the substrate sub-layers are connected, the isolation well region layers in the substrate sub-layers adjacent to the surface of the base extend to the base isolation layer, and the isolation well region layers in the substrate sub-layers are connected with the base isolation layer to form isolation rings; and the device region is positioned in the isolation region surrounded by the isolation ring in the device substrate layer and is isolated by the isolation ring. In a possible implementation manner, the isolation well region layer adjacent to the substrate isolation layer is attached to the substrate isolation layer, and the two adjacent isolation well region layers are attached to each other. In a possible implementation manner, the at least two substrate sub-layers are grown step by step, and the isolation well region layer is formed by performing ion implantation on the current substrate sub-layer after the formation of the current substrate sub-layer and before the growth of the next substrate sub-layer. In a possible implementation manner, the isolation well region layers adjacent to the substrate isolation layer diffuse into the substrate isolation layer, and the isolation well region layers formed later diffuse into the isolation well region layers formed earlier in the two adjacent isolation well region layers. In a possible embodiment, the substrate and the device substrate layer have the same conductivity type, and the spacer ring and the device substrate layer have different conductivity types. In a possible embodiment, the thickness of the substrate sub-layer is less than or equal to a preset thickness, and the preset thickness is 3.5 μm-4 μm. In a possible embodiment, the device region is spaced from the spacer in a longitudinal direction by 0.1-2.3 μm. In a possible embodiment, a lateral interval between the device region and the isolation ring is 0.1-2.5um. In another aspect, the present application provides a method for manufacturing a semiconductor device, comprising: Providing a substrate; forming a substrate isolation layer with one side surface exposed to the surface of the substrate in the substrate; Forming at least two substrate sub-layers arranged in a laminated manner on the surface of the base to obtain a device substrate layer covering the exposed surface of the base isolation layer; after forming each substrate sub-layer, forming an isolation well region layer with two ends penetrating through the substrate sub-layers in the substrate sub-layers to obtain isolation well region layers, connecting the isolation well region layers of the adjacent substrate sub-layers, extending the isolation well region layers in the substrate sub-layers adjacent to the substrate surface to the substrate isolation layer, and connect