CN-121985568-A - Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention improves the reliability of a semiconductor device. The semiconductor device includes a1 st conductive semiconductor layer provided in an active region and a termination region, and a channel stopper provided at a position inside an outer end of the termination region, the channel stopper including a1 st channel stopper groove formed so as to reach from an upper surface of the semiconductor layer to an inside thereof, a1 st conductive impurity portion formed on a surface layer of the semiconductor layer except for the 1 st channel stopper groove, and a 2 nd impurity portion of the 1 st conductive type formed at a bottom of the 1 st channel stopper groove, the 1 st and 2 nd impurity portions having impurity concentrations higher than the semiconductor layer.

Inventors

• GAO JINXIONG

Assignees

• 三菱电机株式会社

Dates

Publication Date

20260505

Application Date

20251017

Priority Date

20241030

Claims (15)

1. 1. A semiconductor device includes an active region forming an element structure, and a termination region surrounding the active region in a plan view, The semiconductor device includes: a semiconductor layer of 1 st conductivity type provided in the active region and the termination region, and A channel stopper portion provided at a position inside an outer end portion of the termination region, The channel stopper includes: a1 st channel-cut groove portion formed so as to reach the inside from the upper surface of the semiconductor layer; a 1 st impurity portion of the 1 st conductivity type formed on a surface layer of the semiconductor layer except for the 1 st channel-cutting groove portion, and The 2 nd impurity part of the 1 st conduction type is formed at the bottom of the 1 st channel cutting groove part, The impurity concentration of the 1 st impurity portion and the impurity concentration of the 2 nd impurity portion are higher than the impurity concentration of the semiconductor layer.
2. 2. The semiconductor device according to claim 1, wherein, The channel stopper further includes a 3 rd impurity portion of the 1 st conductivity type formed on a side surface of the 1 st channel stopper groove portion.
3. 3. The semiconductor device according to claim 2, wherein, The 3 rd impurity portion is connected to the 1 st impurity portion and the 2 nd impurity portion.
4. 4. A semiconductor device according to claim 2 or 3, wherein, The impurity concentration of the 1 st impurity portion and the impurity concentration of the 2 nd impurity portion are higher than the impurity concentration of the 3 rd impurity portion.
5. 5. The semiconductor device according to any one of claims 1 to 4, wherein, The impurity concentration of the 1 st impurity portion and the impurity concentration of the 2 nd impurity portion are 1×10 18 ／cm 3 or more and 1×10 21 ／cm 3 or less.
6. 6. The semiconductor device according to any one of claims 1 to 5, wherein, The semiconductor device further includes a dicing line region surrounding the terminal region in a plan view, The semiconductor layer is arranged in the cutting line area, The semiconductor device further includes an outer groove portion formed so as to reach from an upper surface of the semiconductor layer in the dicing line region to an inside, The depth of the outer groove part is equal to the depth of the 1 st channel cutting groove part.
7. 7. The semiconductor device according to any one of claims 1 to 6, wherein, A metal electrode is not provided on the upper portion of the channel stopper.
8. 8. The semiconductor device according to any one of claims 1 to 7, wherein, The upper portion of the channel stopper is covered with an insulating film without a conductive material.
9. 9. The semiconductor device according to claim 8, wherein, The thickness of the insulating film at the upper portion of the 1 st channel cut groove portion is thicker than the thickness of the insulating film at a portion other than the 1 st channel cut groove portion.
10. 10. The semiconductor device according to any one of claims 1 to 9, wherein, The channel stopper further includes: A2 nd channel-cutting groove portion formed separately from the 1 st channel-cutting groove portion at a position distant from the active region from the 1 st channel-cutting groove portion, and The 4 th impurity part of the 1 st conduction type is formed at the bottom of the 2 nd channel cutting groove part, The 4 th impurity portion has an impurity concentration higher than that of the semiconductor layer.
11. 11. The semiconductor device according to any one of claims 1 to 10, wherein, The channel stopper further includes a 5 th impurity portion of the 1 st conductivity type, the 5 th impurity portion being formed on a surface layer of the semiconductor layer at a position farther from the active region than the 1 st impurity portion, The impurity concentration of the 5 th impurity portion is higher than that of the semiconductor layer.
12. 12. The semiconductor device according to any one of claims 1 to 11, wherein, The semiconductor device further includes a trench type MOS field effect transistor provided in the active region, The depth of the groove in the groove type MOS field effect transistor is equal to the depth of the 1 st channel cutting groove part.
13. 13. The semiconductor device according to any one of claims 1 to 12, wherein, The semiconductor layer is composed of silicon carbide.
14. 14. A method for manufacturing a semiconductor device including an active region forming an element structure and a terminal region surrounding the active region in a plan view, Forming a 1 st channel cut groove portion reaching from an upper surface of the semiconductor layer in the terminal region to an inside with respect to the 1 st conductive type semiconductor layer provided in the active region and the terminal region; Injecting the impurity of the 1 st conductivity type into the surface layer of the semiconductor layer except the 1 st channel cutting groove part and the bottom of the 1 st channel cutting groove part, and And forming a1 st impurity portion of the 1 st conductivity type at a surface layer of a portion of the semiconductor layer other than the 1 st channel cut groove portion and a2 nd impurity portion of the 1 st conductivity type at a bottom of the 1 st channel cut groove portion by activating the impurity after implantation.
15. 15. The method for manufacturing a semiconductor device according to claim 14, wherein, And forming an outer groove part which is a mark used in a manufacturing process and reaches from the upper surface of the semiconductor layer of a scribe line region surrounding the termination region in a plan view, simultaneously with the 1 st channel cut groove part.

Description

Semiconductor device and method for manufacturing semiconductor device Technical Field The present specification discloses a semiconductor device. Background As a method for stabilizing the operation of the termination region of the semiconductor device, a structure in which a structure portion called channel stop is provided at the outermost peripheral portion of the termination region is disclosed (for example, refer to patent literature). Patent document 1 Japanese patent application laid-open No. 2013-138137 The termination structure of the semiconductor device of the related art has room for improvement in the effect of suppressing the depletion layer by channel stopper, moisture resistance, and the like. Disclosure of Invention The technology disclosed in the present specification has been made in view of the above-described problems, and is a technology for improving the reliability of a semiconductor device. The semiconductor device according to the 1 st aspect of the present application includes an active region forming an element structure, and a termination region surrounding the active region in a plan view, wherein the semiconductor device includes a 1 st conductive semiconductor layer provided on the active region and the termination region, and a channel stopper provided on an inner side of an outer end of the termination region, the channel stopper includes a 1 st channel stopper groove formed so as to reach an inside from an upper surface of the semiconductor layer, a 1 st conductive impurity portion formed on a surface layer of the semiconductor layer except for the 1 st channel stopper groove, and a 2 nd impurity portion of the 1 st conductive semiconductor layer formed on a bottom of the 1 st channel stopper groove, wherein an impurity concentration of the 1 st impurity portion and an impurity concentration of the 2 nd impurity portion are higher than an impurity concentration of the semiconductor layer. According to at least aspect 1 of the technology disclosed in the present specification, since extension of the depletion layer from the channel stopper can be suppressed, the semiconductor device is stable in withstand voltage and improved in reliability. Further, the objects, features, aspects and advantages associated with the techniques disclosed in the present specification will become more apparent from the detailed description and drawings shown below. Drawings Fig. 1 is a plan view showing an example of the structure of a semiconductor device according to the embodiment. Fig. 2 is a plan view showing an example of arrangement in a wafer plane of an element region in a manufacturing process. Fig. 3 is a top view of an active region corresponding to region 105 in fig. 1. Fig. 4 is a cross-sectional view corresponding to section A-A' in fig. 3. Fig. 5 is a plan view of an area corresponding to the area 106 in fig. 1. Fig. 6 is a sectional view corresponding to the section B-B' in fig. 5. Fig. 7 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 8 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 9 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 10 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 11 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 12 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 13 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 14 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 15 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 16 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 17 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 18 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 19 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 20 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 21 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to the embodiment. Fig. 22 is a