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CN-121985570-A - Super junction semiconductor device and manufacturing method thereof

CN121985570ACN 121985570 ACN121985570 ACN 121985570ACN-121985570-A

Abstract

The invention provides a super junction semiconductor device and a manufacturing method thereof, wherein the super junction semiconductor device comprises a first conductive type substrate and a first conductive type epitaxial layer, a first groove is arranged in the first conductive type epitaxial layer, a second conductive type epitaxial layer is arranged on the inner wall of the first groove, a first dielectric layer is arranged in the first groove, a part of the second conductive type epitaxial layer on the same side of the top of each first groove is removed to form a second groove, a grid groove is formed on the upper part in the second groove, a first dielectric layer is left below the grid groove, a grid oxide layer is arranged on the side wall of the grid groove, grid polysilicon is arranged in the grid groove, a second conductive type well region is arranged on the top of the first conductive type epitaxial layer on the two sides of the first groove, a heavily doped first conductive type injection region is formed on the top of the second conductive type well region on the same side of each first groove close to the grid groove, and the device provided by the method can bear higher withstand voltage and improve working frequency.

Inventors

  • DING LEI
  • TENG ZHIGANG

Assignees

  • 无锡商甲半导体有限公司

Dates

Publication Date
20260505
Application Date
20260205

Claims (10)

  1. 1. The super junction semiconductor device is characterized by comprising a first conductive type substrate (1), wherein a first conductive type epitaxial layer (2) is arranged on the first conductive type substrate (1), the surface of the first conductive type epitaxial layer (2) facing away from the first conductive type substrate (1) is a first main surface, and the surface of the first conductive type substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface; A first groove (3) is arranged in the first conductive type epitaxial layer (2), and the first groove (3) is a deep groove and is positioned in an active region of the device and arranged in parallel at intervals; the inner wall of the first groove (3) is provided with a second conductive type epitaxial layer (4), and the first groove (3) is provided with a first dielectric layer (5); The second conductive type epitaxial layer (4) on the same side of the top of each first groove (3) is removed, a second groove (6) is formed, the second groove (6) is a shallow groove, the depth is smaller than that of the first groove (3), a grid groove (7) is formed at the upper part in the second groove (6), a first dielectric layer (5) is reserved below the grid groove (7), a grid oxide layer (8) is arranged on the first main surface and the side wall of the grid groove (7), and grid polysilicon (901) is arranged in the grid groove (7); The top of the first conductive type epitaxial layer (2) at two sides of each first groove (3) is provided with a second conductive type well region (10), a heavily doped first conductive type injection region (11) is formed at the top in the second conductive type well region (10) at the same side of each first groove (3) close to the gate groove (7), a heavily doped second conductive type injection region (14) is formed in the middle of the second conductive type well region (10) between the adjacent first grooves (3), and the heavily doped second conductive type injection region (14) extends to the lower part of the heavily doped first conductive type injection region (11); A second dielectric layer (12) is arranged on the first main surface; A source metal (15) and a grid metal are arranged on the second dielectric layer (12); The source metal (15) is connected with the heavily doped first conductive type injection region (11) and the heavily doped second conductive type injection region (14) through a source contact hole (13) penetrating through the second dielectric layer (12); The gate metal is connected with the gate polysilicon (901) through a gate contact hole penetrating through the second dielectric layer (12); A drain metal is provided on the second main surface.
  2. 2. The superjunction semiconductor device of claim 1, wherein, The width of the gate trench (7) is 0.1-0.5 mu m.
  3. 3. The superjunction semiconductor device of claim 1, wherein, The height of a section of the first dielectric layer (5) below the grid groove (7) is 0.2-2 mu m.
  4. 4. The superjunction semiconductor device of claim 1, wherein, The width of the grid polysilicon (901) is 0.1-0.4 mu m.
  5. 5. The superjunction semiconductor device of claim 1, wherein, The height of the grid polysilicon (901) is 0.5-2.5 mu m.
  6. 6. A method of manufacturing a super junction semiconductor device according to any one of claims 1 to 5, comprising the steps of: Step S1, providing a first conductive type substrate (1), and growing a first conductive type epitaxial layer (2) on the first conductive type substrate (1), wherein the surface of the first conductive type epitaxial layer (2) facing away from the first conductive type substrate (1) is a first main surface, and the surface of the first conductive type substrate (1) facing away from the first conductive type epitaxial layer (2) is a second main surface; step S2, etching a first groove (3) in the first conductive type epitaxial layer (2), wherein the first groove (3) is a deep groove and is positioned in an active area of the device and arranged in parallel at intervals; step S3, depositing a second conductive type epitaxial layer (4) on the first main surface and the inner wall of the first groove (3); S4, depositing a first dielectric layer (5) on the first main surface, wherein the first dielectric layer (5) is filled with the first groove (3); step S5, removing the first dielectric layer (5) and the second conductive type epitaxial layer (4) on the first main surface by CMP; Step S6, selectively etching the second conductive type epitaxial layer (4), and forming a second groove (6) on the same side of the top of each first groove (3), wherein the second groove (6) is a shallow groove, and the depth of the second groove is smaller than that of the first groove (3); Step S7, depositing a first dielectric layer (5) on the first main surface again, wherein the first dielectric layer (5) fills the second groove (6); Step S8, removing the first dielectric layer (5) on the first main surface by CMP; step S9, selectively etching the first dielectric layers (5), and forming a grid groove (7) on the same side of the top of each first groove (3), wherein the depth of the grid groove (7) is smaller than that of the first grooves (3), and a section of first dielectric layer 5 is reserved below the grid groove (7); Step S10, a gate oxide layer (8) is grown on the first main surface and the side wall of the gate trench (7); step S11, depositing conductive polysilicon (9) in the first main surface and the gate trench (7); Step S12, etching the conductive polysilicon (9) of the first main surface, and forming gate polysilicon (901) in the gate trench (7); S13, injecting second conductivity type impurities into the first main surface and pushing the wells, and forming second conductivity type well regions (10) on the tops of the first conductivity type epitaxial layers (2) on the two sides of the first groove (3); Step S14, selectively implanting first conductivity type impurities and annealing, and forming a heavily doped first conductivity type implantation region (11) at the inner top of the second conductivity type well region (10) on the same side of each first trench (3) close to the gate trench (7); Step S15, depositing a second dielectric layer (12) on the first main surface; Step S16, forming a source contact hole (13) and a gate contact hole on the first main surface by selective etching, wherein the source contact hole (13) extends to the position below the first conductive type injection region (11), performing second conductive type impurity injection through the source contact hole (13) and annealing, forming a heavily doped second conductive type injection region (14) in the middle of the second conductive type well region (10) between the adjacent first trenches (3), and the heavily doped second conductive type injection region (14) extends to the position below the heavily doped first conductive type injection region (11); Step S17, depositing metal on the first main surface and selectively etching to form source metal (15) and gate metal; Step S18, depositing a drain metal on the second main surface.
  7. 7. The method of manufacturing a super junction semiconductor device as claimed in claim 6, wherein, The width of the gate trench (7) is 0.1-0.5 mu m.
  8. 8. The method of manufacturing a super junction semiconductor device as claimed in claim 6, wherein, The height of a section of the first dielectric layer 5 below the gate trench (7) is 0.2-2 mu m.
  9. 9. The method of manufacturing a super junction semiconductor device as claimed in claim 6, wherein, The width of the grid polysilicon (901) is 0.1-0.4 mu m.
  10. 10. The method of manufacturing a super junction semiconductor device as claimed in claim 6, wherein, The height of the grid polysilicon (901) is 0.5-2.5 mu m.

Description

Super junction semiconductor device and manufacturing method thereof Technical Field The invention relates to a semiconductor power device, in particular to a super junction semiconductor device and a manufacturing method thereof. Background The traditional super junction semiconductor device is provided with P-type epitaxy and N-type epitaxy which are alternately distributed, and the P-type epitaxy is simply subjected to P/N junction voltage resistance, the P-type epitaxy needs higher P doping concentration to be matched with the N-type epitaxy so as to achieve the required optimal voltage resistance value, but thicker P doping can lead to higher reverse recovery charge, thereby influencing the dynamic power consumption, the reaction speed and the working frequency of the device. The super junction semiconductor device works in a high-frequency scene, most of the existing structures are plane grid electrodes or common trench grid electrodes, and the grid electrodes have larger electric charges, so that the working frequency of the device is not improved. Disclosure of Invention In order to solve at least one technical problem in the prior art, the embodiment of the invention provides a super junction semiconductor device and a manufacturing method thereof, which can bear higher withstand voltage, reduce switching loss and improve the working frequency of the device. In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the invention is as follows: in a first aspect, an embodiment of the present invention provides a super junction semiconductor device, including a first conductive type substrate, on which a first conductive type epitaxial layer is disposed, where a surface of the first conductive type epitaxial layer facing away from the first conductive type substrate is a first main surface, and a surface of the first conductive type substrate facing away from the first conductive type epitaxial layer is a second main surface; The first groove is a deep groove and is positioned in an active area of the device and arranged in parallel at intervals; the inner wall of the first groove is provided with a second conductive type epitaxial layer, and the first groove is internally provided with a first dielectric layer; The second groove is a shallow groove with the depth smaller than that of the first groove, a grid groove is formed at the upper part in the second groove, a first dielectric layer is left below the grid groove, a grid oxide layer is arranged on the first main surface and the side wall of the grid groove, and grid polysilicon is arranged in the grid groove; The top of the first conductive type epitaxial layer at two sides of the first groove is provided with a second conductive type well region; forming a heavily doped first conductivity type injection region on the top in the second conductivity type well region on the same side of each first trench as the gate trench; forming a heavily doped second conductivity type injection region in the middle of the second conductivity type well region between the adjacent first trenches; A second dielectric layer is arranged on the first main surface; A source electrode metal and a grid electrode metal are arranged on the second dielectric layer; the source metal is connected with the heavily doped first conductive type injection region and the heavily doped second conductive type injection region through a source contact hole penetrating through the second dielectric layer; The gate metal is connected with the gate polysilicon through a gate contact hole penetrating through the second dielectric layer; A drain metal is provided on the second main surface. Further, the width of the gate trench is 0.1 μm to 0.5 μm. Further, the height of a section of the first dielectric layer 5 below the gate trench is 0.2 μm to 2 μm. Further, the width of the grid polysilicon is 0.1-0.4 mu m. Further, the height of the grid polysilicon is 0.5-2.5 μm. In a second aspect, embodiments of the present invention provide a method for manufacturing a super junction semiconductor device as described above, comprising the steps of: step S1, providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate, wherein the surface of the first conductive type epitaxial layer, which is away from the first conductive type substrate, is a first main surface, and the surface of the first conductive type substrate, which is away from the first conductive type epitaxial layer, is a second main surface; Step S2, etching a first groove in the epitaxial layer of the first conductivity type to form a first groove, wherein the first groove is a deep groove and is positioned in an active area of the device and arranged in parallel at intervals; step S3, depositing a second conductive type epitaxial layer on the first main surface and the inner wall of the first groove; step S4, a first diele