CN-121985576-A - Structure and method for improving reliability of high-resistance region in metal gate process

CN121985576ACN 121985576 ACN121985576 ACN 121985576ACN-121985576-A

Abstract

The invention discloses a structure for improving the reliability of a high-resistance region in a metal gate process, wherein a high resistance is formed at the top of shallow trench isolation formed with a metal gate. The high resistance and the adjacent pseudo-active regions have a first lateral spacing therebetween, and the first lateral spacing is used for adjusting the pattern density of the pseudo-active regions and enabling the height and uniformity of the shallow trench isolation to meet the requirements. The interlayer film has a first thickness and the first thickness satisfies a process requirement of a contact hole passing through the interlayer film. The interlayer film is divided into first and second interlayer sub-films. The high resistance is located between the first and second interlayer sub-films, the first interlayer sub-film having a second thickness. The second thickness is used for adjusting the second longitudinal spacing between the high resistance and the adjacent pseudo-active area, and ensuring that the minimum spacing between the high resistance and the adjacent pseudo-active area meets the voltage withstanding requirement under the condition that the first transverse spacing is not increased. The invention also discloses a method for improving the reliability of the high-resistance region in the metal gate process.

Inventors

TIAN ZHI
SHAN DUO
CHEN HAOYU
SHAO HUA

Assignees

上海华力集成电路制造有限公司

Dates

Publication Date: 20260505
Application Date: 20260128

Claims (14)

1. The utility model provides a structure for improving high resistance region reliability in metal gate technology which characterized in that, the structure of high resistance region includes: A plurality of shallow trench isolations formed in a semiconductor substrate and a plurality of dummy active regions between the shallow trench isolations, wherein a metal gate is formed on top of a part of the shallow trench isolations and a high resistance composed of a TiN layer is formed on top of the metal gate; At least partial areas on the periphery of the shallow trench isolation at the bottom of the high resistor are provided with the pseudo active areas, a first transverse interval is arranged between the high resistor and the adjacent pseudo active areas, the smaller the first transverse interval is, the higher the pattern density of the pseudo active areas is, and the larger the area ratio of the pseudo active areas and the shallow trench isolation of each area of the high resistor is, the area ratio of the pseudo active areas and the shallow trench isolation is required to ensure that the height and the uniformity of the shallow trench isolation meet the requirements; An interlayer film covering the shallow trench isolations and the tops of the dummy active regions, the interlayer film having a first thickness, the interlayer film being divided into a first interlayer sub-film and a second interlayer sub-film on the tops of the shallow trench isolations formed with the high resistances; the first interlayer sub-film covers the metal gate, and has a second thickness outside the metal gate; The second interlayer sub-film covers the high resistance, and has a third thickness outside the high resistance, wherein the first thickness is the sum of the second thickness and the third thickness; The second thickness is used for adjusting a second longitudinal spacing between the high resistance and the adjacent pseudo active region, and the second longitudinal spacing is increased by increasing the second thickness under the condition of ensuring that the first transverse spacing is not increased, so that the minimum spacing between the high resistance and the adjacent pseudo active region meets the voltage withstanding requirement.
2. The structure of claim 1, wherein each of the high-resistance regions has a stripe-shaped structure, and first contact holes penetrating through the second interlayer sub-film are formed at both ends of the high-resistance region.
3. The structure for improving reliability of high resistance region in metal gate process of claim 2, further comprising a substrate extraction region; the substrate lead-out area is in an annular structure, and each high resistor is positioned in the annular area of the substrate lead-out area; the semiconductor substrate has a second conductivity type doping, the substrate lead-out region has a second conductivity type heavy doping, and a second contact hole penetrating the interlayer film is formed on top of the substrate lead-out region.
4. The structure of claim 1, wherein a gate dielectric layer is formed on the bottom of the metal gate.
5. The structure of claim 4, wherein the high resistance region reliability in the metal gate process is improved by: the gate dielectric layer material comprises a high dielectric constant material.
6. The structure of claim 2, wherein said high resistance is located directly above said metal gate and said high resistance further extends outside said metal gate.
7. The structure of claim 2, wherein said high-resistance region is located outside a device cell region in which said metal gate is formed on a surface of said semiconductor substrate and a third contact hole is formed on top of said metal gate through said interlayer film.
8. The method for improving the reliability of the high-resistance region in the metal gate process is characterized by comprising the following steps of: The method comprises the steps of forming shallow trench isolation in a semiconductor substrate, forming an active region by the semiconductor substrate surrounded by the shallow trench isolation, forming the shallow trench isolation by etching and filling shallow trenches and chemical mechanical polishing, wherein the active region between the shallow trench isolation is a pseudo-active region in a high-resistance region, wherein the pseudo-active region is used for adjusting the pattern density in the high-resistance region, the larger the pattern density of the pseudo-active region is, the larger the area ratio of the pseudo-active region and the shallow trench isolation of each region of the high-resistance region is, and the area ratio of the pseudo-active region and the shallow trench isolation meets the chemical mechanical polishing load requirement and thereby ensures that the height and uniformity of the shallow trench isolation meet the requirement; Forming a metal gate on the surface of the shallow trench isolation with high resistance at the top of the high-resistance region; Forming a first interlayer sub-film which covers the shallow trench isolation and the top of each pseudo active region and covers the metal gate, wherein the first interlayer sub-film has a second thickness outside the metal gate; The high resistance is formed by a TiN layer, the high resistance is positioned at the top of the corresponding metal gate, at least part of the peripheral side of the shallow trench isolation at the bottom of the high resistance is provided with the pseudo active region, a first transverse interval is arranged between the high resistance and the adjacent pseudo active region, the first transverse interval is used for adjusting the pattern density of the pseudo active region, the smaller the first transverse interval is, the larger the pattern density of the pseudo active region is, the second thickness is used for adjusting the second longitudinal interval between the high resistance and the adjacent pseudo active region, and the second longitudinal interval is increased by increasing the second thickness under the condition of ensuring that the first transverse interval is not increased, so that the minimum interval between the high resistance and the adjacent pseudo active region meets the pressure-resistant requirement; Forming a second interlayer sub-film, wherein the first interlayer sub-film and the second interlayer sub-film are overlapped to form an interlayer film, the second interlayer sub-film covers the high resistance, the second interlayer sub-film has a third thickness outside the high resistance, the first thickness is the sum of the second thickness and the third thickness, and the first thickness meets the process requirement of forming a contact hole penetrating through the interlayer film.
9. The method of improving reliability of a high resistance region in a metal gate process of claim 8, further comprising subsequently: and forming a contact hole, wherein each high-resistance strip-shaped structure comprises a first contact hole positioned at two ends of the high-resistance strip-shaped structure, and the first contact hole penetrates through the second interlayer sub-film.
10. The method for improving reliability of high resistance region in metal gate process of claim 10, further comprising a substrate extraction region; the substrate lead-out area is in an annular structure, and each high resistor is positioned in the annular area of the substrate lead-out area; the semiconductor substrate has a second conductivity type doping, the substrate lead-out region has a second conductivity type heavy doping, and a second contact hole penetrating the interlayer film is formed on top of the substrate lead-out region.
11. The method of improving reliability of high resistance region in metal gate process of claim 8, wherein a gate dielectric layer is further formed on bottom of the metal gate.
12. The method for improving the reliability of a high resistance region in a metal gate process of claim 11, wherein: the gate dielectric layer material comprises a high dielectric constant material.
13. The method of improving reliability of a high resistance region in a metal gate process of claim 9 wherein said high resistance is located directly above said metal gate and said high resistance further extends outside said metal gate.
14. The method for improving reliability of a high resistance region in a metal gate process as claimed in claim 9, wherein said high resistance region is located outside a device cell region in which said metal gate is formed on a surface of said semiconductor substrate and a third contact hole is formed on top of said metal gate through said interlayer film.

Description

Structure and method for improving reliability of high-resistance region in metal gate process Technical Field The present invention relates to the field of semiconductor integrated circuit fabrication, and more particularly, to a structure for improving the reliability of a high-resistance region in a metal gate process. The invention also relates to a method for improving the reliability of the high-resistance region in the metal gate process. Background At present, 28 nanometers and above are used as a gate electrode, namely a Metal Gate (MG), so that the conventional polysilicon resistor cannot be provided, titanium nitride (TiN) is singly used as high resistance (HiR) in a metal gate electrode process, and after the metal gate electrode is formed, a dielectric layer is grown, and then deposition of titanium nitride is carried out, so that the high resistance can be provided. In practice, the resistor needs to be placed above the metal gate to prevent the instability of the length of the titanium nitride caused by the recess after the interlayer dielectric layer is polished. When the resistor is used in a peripheral protection region with a large area, a problem is how to ensure that the resistor has enough density of an active region, so that chemical mechanical polishing of shallow trench isolation (shallow trench isolation, STI) after the active region can be normally performed. At present, the dummy pattern of the active region is inserted around the high-resistance region, namely the dummy active region is inserted, and the closer the distance between the dummy active region and the high resistance is, the pattern density of the dummy active region is increased, which is beneficial to the process of the active region and the height and uniformity of the shallow trench isolation region below the high-resistance region. In the esd protection circuit for input/output, a titanium nitride resistor is used as a resistor providing RC delay, in which a transient state has a high voltage region of up to 200V in the mechanical discharge mode, which causes leakage or even breakdown between the adjacent active region and the high resistor. In the prior art, to solve this problem, the distance between the dummy pattern of the active region and the high resistance needs to be increased. Thus, there is a conflict between the more recent active region dummy pattern required for cmp in the shallow trench isolation region and the more distant active region dummy required for preventing leakage in the high resistance region. As shown in fig. 1, is a layout of a structure of an existing high-resistance region, as shown in fig. 2, is a schematic cross-sectional structure of the existing high-resistance region along a line AA' in fig. 1, and the structure of the existing high-resistance region includes: A plurality of shallow trench isolations 102 formed in a semiconductor substrate 101 and a plurality of dummy active regions located between the shallow trench isolations 102. In fig. 2, a P-type doped region 103 is formed in a surface region of the dummy active region, and the pattern of the dummy active region is the same as that of the doped region 103. A metal gate 105 is formed on top of a part of the shallow trench isolation 102 and a high resistance 107 composed of a TiN layer is formed on top of the metal gate 105. At least a partial region on the peripheral side of the shallow trench isolation 102 at the bottom of the high resistance 107 has the dummy active region. As shown in fig. 1, each of the high resistors 107 has the dummy active regions on three sides. An interlayer film 106 covers the tops of the shallow trench isolations 102 and the dummy active regions, the interlayer film 106 covers the metal gate 105, and the high resistance 107 is inserted into the interlayer film 106 on top of the metal gate 105. As shown in fig. 1, each of the high resistances 107 has a stripe structure. Returning to fig. 2, first contact holes 108a are formed at the top of both ends of the high resistance 107, respectively. As shown in fig. 1, further includes a substrate extraction region 104. The substrate lead-out area 104 has a ring-shaped structure, and each high resistance 107 is located inside the ring-shaped area of the substrate lead-out area 104. Returning to fig. 2, the semiconductor substrate 101 has P-type doping, the substrate lead-out region 104 has P-type heavy doping, and a second contact hole 108b penetrating the interlayer film 106 is formed on top of the substrate lead-out region 104. The high resistance 107 is located directly above the metal gate 105, and the high resistance 107 also extends to the outside of the metal gate 105. As shown in fig. 2, since the periphery of the high-resistance region is a high-voltage region in which a high-voltage device is formed, the high voltage of the high-voltage region easily causes breakdown as indicated by reference numeral 201 between the high resistance 107 and the