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CN-121985578-A - High-power SIC MOSFET SSC switch module utilizing auxiliary substrate

CN121985578ACN 121985578 ACN121985578 ACN 121985578ACN-121985578-A

Abstract

The present invention relates to a high power SIC MOSFET SSC power switch module using an auxiliary substrate, and provides a structure of a high power SIC MOSFET SSC power switch module using an auxiliary substrate, which increases a pattern of the SSC power switch module transmitting a large current while providing a high-efficiency heat dissipation characteristic, and eliminates an influence caused by a leakage current, a parasitic voltage, etc. by applying an auxiliary substrate insulated from the SSC substrate, thereby improving a high input impedance electrical characteristic of a gate terminal of the SIC MOSFET module, and enabling miniaturization of the size of the high power SIC MOSFET module, and enabling a wiring terminal led to the outside to be arranged in a uniaxial direction.

Inventors

  • JIN YUANSHI

Assignees

  • 北一半导体科技(广东)有限公司

Dates

Publication Date
20260505
Application Date
20260126

Claims (6)

  1. 1. A high-power SIC MOSFET SSC switch module utilizing an auxiliary substrate is characterized in that, The high-power SIC MOSFET SSC switch module comprises an SSC substrate (100), A first Vss pattern (102) and a second Vss pattern (106) are provided at both right and left sides of a component arrangement surface of the SSC substrate (100), Vdd pattern (104) is arranged between the first Vss pattern (102) and the second Vss pattern (106), An output Pout pattern (124) of a half-bridge circuit is arranged between the first Vss pattern (102) and the second Vss pattern (106) and below the Vdd pattern (104), A first Kelvin terminal relay pattern (112) is provided between the first Vss pattern (102) and the Vdd pattern (104), A first Kelvin terminal pattern (108) and a second Kelvin terminal pattern (110) are formed in the Vdd pattern (104), a first gate pattern (114) and a second gate pattern (116) are formed at the lower end of the Vdd pattern (104), A gate rail pattern (122) is formed between the Vdd pattern (104) and the Pout pattern (124), a second kelvin terminal relay pattern (118) and a first gate relay pattern (120) extend to a lower end of the first Vss pattern (102) at a left side of the first Vss pattern (102), A second gate relay pattern (126) and a third Kelvin terminal relay pattern (130) are arranged in the middle of the Pout pattern (124), At the lower end of the SSC substrate (100), the Vdd pattern (104) extends so as to connect terminals, and is formed with a first Kelvin terminal connection terminal (134) and a first gate connection terminal (136), A fourth Kelvin terminal relay pattern (128) is provided between the Pout pattern (124) and the first gate connection terminal (136) and the connection terminal (138), On the right side of the fourth Kelvin terminal relay pattern (128) and the connection terminal (140), a Pout pattern (124) is formed to extend so as to connect the connection terminals, On the right side of the Pout pattern (124) formed by extension, an NTC1 connection terminal (142), a second kelvin terminal connection terminal (144), a second gate connection terminal (146), an NTC2 connection terminal (148), and an ntc_com connection terminal (150) are formed, On the right side of the ntc_com connection terminal (150), the Pout pattern (124) extends so that the connection terminals are connected.
  2. 2. The high power SIC MOSFET SSC switching module of claim 1 utilizing an auxiliary substrate, wherein, On the SSC substrate (100), A first Kelvin terminal auxiliary substrate (108 s) is attached to the first Kelvin terminal pattern (108), a second Kelvin terminal auxiliary substrate (110 s) is attached to the second Kelvin terminal pattern (110), a first gate auxiliary substrate (114 s) is attached to the first gate pattern (114), a second gate auxiliary substrate (116 s) is attached to the second gate pattern (116), a second gate relay auxiliary substrate (126 s) is attached to the second gate relay pattern (126), On the right side Vdd pattern (104) of the first gate sub-substrate (114 s), SIC MOSFET1 (200) and SIC MOSFET2 (202) are arranged with the gate terminal and kelvin terminal respectively facing the first gate sub-substrate (114 s) and attached to Vdd pattern (104) respectively, making the drain conductive, On the left Vdd pattern (104) of the second gate sub-substrate (116 s), SIC MOSFET3 (204) and SIC MOSFET4 (206) are arranged with the gate terminal and kelvin terminal respectively facing the second gate sub-substrate (116 s) and attached to Vdd pattern (104) respectively, making the drain conductive, On the Vdd pattern (104) on the right side of the second gate auxiliary substrate (116 s), SIC MOSFET5 (208) and SIC MOSFET6 (210) are arranged with the gate terminal and kelvin terminal respectively facing the second gate auxiliary substrate (116 s) and attached to Vdd pattern (104) respectively, making the drain conductive, On the Pout pattern (124) on the left side of the second gate relay auxiliary substrate (126 s), the SIC MOSFET7 (212) and the SIC MOSFET8 (214) are arranged in a direction in which the gate terminal and the kelvin terminal are opposed to each other, Between the second gate relay auxiliary substrate (126 s) and the SIC MOSFET8 (214), the SIC MOSFET9 (216) is arranged with the gate terminal and the Kelvin terminal facing downward, and is attached to the Pout pattern (124), respectively, to make the drain conductive, On the Pout pattern (124) on the right side of the second gate relay auxiliary substrate (126 s), the SIC MOSFET10 (218) and the SIC MOSFET11 (220) are arranged in a direction in which the gate terminal and the kelvin terminal are opposite to each other, Between the second gate relay auxiliary substrate (126 s) and the SIC MOSFET11 (220), the SIC MOSFET12 (222) is arranged with the gate terminal and the Kelvin terminal facing downward, and is attached to the Pout pattern (124), respectively, to make the drain conductive, One end of an NTC1 (224) is connected to the pattern in which the NTC1 connection terminal (142) extends, one end of an NTC2 (226) is connected to the NTC2 connection terminal (148), and the other ends of the NTC1 and NTC2 are connected to the ntc_com connection terminal (150).
  3. 3. The high power SIC MOSFET SSC switching module of claim 2 utilizing an auxiliary substrate, wherein, On the SSC substrate (100), The drain terminal of the SIC MOSFET is bonded to each pattern by soldering or silver epoxy sintering, making the drain terminal conductive, The NTC thermistor is fixedly attached to the corresponding pattern by soldering or silver epoxy sintering, The auxiliary substrate is fixedly attached to the corresponding pattern by an insulating adhesive.
  4. 4. The high power SIC MOSFET SSC switching module of claim 2 utilizing an auxiliary substrate, wherein, On the SSC substrate (100), The source terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) are connected in parallel by a plurality of bond wires, and the bond wires extend to and bond with the Pout pattern (124), The source terminals of the SIC MOSFET3 (204) and the SIC MOSFET4 (206) are connected in parallel by a plurality of bonding wires, and the bonding wires extend to the Pout pattern (124) and are bonded, The source terminals of the SIC MOSFET5 (208) and the SIC MOSFET6 (210) are connected in parallel by a plurality of bonding wires, and the bonding wires extend to the Pout pattern (124) and are bonded, The Kelvin terminal of the SIC MOSFET1 (200) is bonded to the first Kelvin terminal auxiliary substrate (108 s), The Kelvin terminal of the SIC MOSFET3 (204) is bonded to the second Kelvin terminal auxiliary substrate (110 s), The first Kelvin terminal auxiliary substrate (108 s) and the second Kelvin terminal auxiliary substrate (110 s) are connected by bonding, The first Kelvin terminal auxiliary substrate (108 s) is bonded to a first Kelvin terminal relay pattern (112), The first Kelvin terminal relay pattern (112) is bonded to the second Kelvin terminal relay pattern (118), and the second Kelvin terminal relay pattern (118) is bonded to the first Kelvin terminal connection terminal (134), The gate terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) are bonded to the first gate auxiliary substrate (114 s), The first gate auxiliary substrate (114 s) is bonded to a gate rail pattern (122), The gate terminals of SIC MOSFET3 (204), SIC MOSFET4 (206), SIC MOSFET5 (208) and SIC MOSFET6 (210) are bonded to the second gate auxiliary substrate (116 s), respectively, The second gate auxiliary substrate (116 s) is bonded to the gate rail pattern (122), The gate rail pattern (122) is bonded to the first gate relay pattern (120), The first gate relay pattern (120) is bonded to the first gate connection terminal (136), The source terminals of the SIC MOSFETs 7 (212) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend to the first Vss pattern (102) and are bonded, The source terminals of SIC MOSFET8 (214) and SIC MOSFET9 (216) are connected in parallel by a plurality of bond wires to transmit a large current, and the bond wires extend to the first Vss pattern (102) and are bonded, The source terminals of the SIC MOSFETs 10 (218) are connected in parallel by a plurality of bond wires, and the bond wires extend to the second Vss pattern (106) and are bonded, The source terminals of the SIC MOSFET11 (220) and the SIC MOSFET12 (222) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend to the second Vss pattern (106) and are bonded, The Kelvin terminal of the SIC MOSFET9 (216) is bonded to a third Kelvin terminal relay pattern (130) via a fourth Kelvin terminal relay pattern (128), The third Kelvin terminal relay pattern (130) is bonded to a second Kelvin terminal connection terminal (144), The kelvin terminal of the SIC MOSFET12 (222) is bonded to the second kelvin terminal connection terminal (144), The gate terminals of SIC MOSFET7 (212), SIC MOSFET8 (214) and SIC MOSFET9 (216) are bonded to the second gate relay auxiliary substrate (126 s), respectively, The gate terminals of SIC MOSFET10 (218), SIC MOSFET11 (220) and SIC MOSFET12 (222) are bonded to the second gate relay auxiliary substrate (126 s), respectively, The second gate relay auxiliary substrate (126 s) is bonded to the second gate connection terminal (146).
  5. 5. The high power SIC MOSFET SSC switching module of claim 1 utilizing an auxiliary substrate, wherein, On the SSC substrate (100), A first Kelvin terminal auxiliary substrate (108 s) is attached to the first Kelvin terminal pattern (108), a second Kelvin terminal auxiliary substrate (110 s) is attached to the second Kelvin terminal pattern (110), a first gate auxiliary substrate (114 s) is attached to the first gate pattern (114), a second gate auxiliary substrate (116 s) is attached to the second gate pattern (116), a second gate relay auxiliary substrate (126 s) is attached to the second gate relay pattern (126), On the right side Vdd pattern (104) of the first gate sub-substrate (114 s), SIC MOSFET1 (200) and SIC MOSFET2 (202) are arranged with gate terminals and kelvin terminals facing the first gate sub-substrate (114 s) and attached to Vdd pattern (104), respectively, to make the drain conductive, On the first gate auxiliary substrate (114 s), gate resistors corresponding to SIC MOSFET1 (200) and SIC MOSFET2 (202) are respectively attached, On the left Vdd pattern (104) of the second gate auxiliary substrate (116 s), SIC MOSFET3 (204) and SIC MOSFET4 (206) are arranged with gate terminals and kelvin terminals facing the second gate auxiliary substrate (116 s) and attached to Vdd pattern (104), respectively, to make the drain conductive, On the Vdd pattern (104) on the right side of the second gate auxiliary substrate (116 s), the SIC MOSFET5 (208) and the SIC MOSFET6 (210) are arranged with the gate terminal and the kelvin terminal facing the second gate auxiliary substrate (116 s) and attached to the Vdd pattern (104), respectively, to make the drain conductive, On the second gate auxiliary substrate (116 s), gate resistances corresponding to SIC MOSFET3 (204), SIC MOSFET4 (206), SIC MOSFET5 (208) and SIC MOSFET6 (210) are attached by soldering or silver epoxy sintering to conduct, On the Pout pattern (124) on the left side of the second gate relay auxiliary substrate (126 s), the SIC MOSFET7 (212) and the SIC MOSFET8 (214) are arranged in a direction in which the gate terminal and the kelvin terminal are opposed to each other, Between the second gate relay auxiliary substrate (126 s) and the SIC MOSFET8 (214), the SIC MOSFET9 (216) is arranged with the gate terminal and the Kelvin terminal facing downward, and is attached to the Pout pattern (124) to make the drain conductive, On the Pout pattern (124) on the right side of the second gate relay auxiliary substrate (126 s), the SIC MOSFET10 (218) and the SIC MOSFET11 (220) are arranged in a direction in which the gate terminal and the kelvin terminal are opposite to each other, Between the second gate relay auxiliary substrate (126 s) and the SIC MOSFET11 (220), the SIC MOSFET12 (222) is arranged with the gate terminal and the Kelvin terminal facing downward, and is attached to the Pout pattern (124) to make the drain conductive, On the second gate relay auxiliary substrate (126 s), gate resistances corresponding to the SIC MOSFET7 (212), the SIC MOSFET8 (214), the SIC MOSFET9 (216), the SIC MOSFET10 (218), the SIC MOSFET11 (220) and the SIC MOSFET12 (222) are respectively attached by soldering or silver epoxy sintering to conduct, One end of an NTC1 (224) is connected to the pattern in which the NTC1 connection terminal (142) extends, one end of an NTC2 (226) is connected to the NTC2 connection terminal (148), and the other ends of the NTC1 and NTC2 are connected to the ntc_com connection terminal (150).
  6. 6. The high power SIC MOSFET SSC switching module of claim 5 utilizing an auxiliary substrate, wherein, On the SSC substrate (100), The source terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend to and bond with the Pout pattern (124), The source terminals of the SIC MOSFET3 (204) and the SIC MOSFET4 (206) are connected in parallel by a plurality of bonding wires, and the bonding wires extend to the Pout pattern (124) and are bonded, The source terminals of the SIC MOSFET5 (208) and the SIC MOSFET6 (210) are connected in parallel by a plurality of bonding wires, and the bonding wires extend to the Pout pattern (124) and are bonded, The Kelvin terminal bond connection of the SIC MOSFET1 (200) to a first Kelvin terminal auxiliary substrate (108 s), the Kelvin terminal bond connection of the SIC MOSFET3 (204) to a second Kelvin terminal auxiliary substrate (110 s), the first Kelvin terminal auxiliary substrate (108 s) and the second Kelvin terminal auxiliary substrate (110 s) being connected by a bond, the first Kelvin terminal auxiliary substrate (108 s) being connected to a first Kelvin terminal relay pattern (112), the first Kelvin terminal relay pattern (112) being bonded to a second Kelvin terminal relay pattern (118), and the second Kelvin terminal relay pattern (118) being connected to a first Kelvin terminal connection terminal (134), The gate terminals of SIC MOSFET1 (200) and SIC MOSFET2 (202) are respectively bonded and connected to respective gate resistors fixed on a first gate auxiliary substrate (114 s), the first gate auxiliary substrate (114 s) is bonded to a gate rail pattern (122), The gate terminals of SIC MOSFET3 (204), SIC MOSFET4 (206), SIC MOSFET5 (208) and SIC MOSFET6 (210) are respectively bonded to respective gate resistors fixed to a second gate auxiliary substrate (116 s), the second gate auxiliary substrate (116 s) being bonded to the gate rail pattern (122), The gate rail pattern (122) is connected to a first gate relay pattern (120) in a bonding manner, the first gate relay pattern (120) is connected to a first gate connection terminal (136) in a bonding manner, The source terminals of the SIC MOSFETs 7 (212) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend to the first Vss pattern (102) and are bonded, The source terminals of the SIC MOSFET8 (214) and the SIC MOSFET9 (216) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend to the first Vss pattern (102) on the side of the Pout pattern (124) and are bonded, The source terminals of the SIC MOSFETs 10 (218) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend to the second Vss pattern (106) and are bonded, The source terminals of the SIC MOSFET11 (220) and the SIC MOSFET12 (222) are connected in parallel by a plurality of bonding wires to transmit a large current, and the bonding wires extend and are bonded to the second Vss pattern (106), The Kelvin terminal of the SIC MOSFET9 (216) is bonded to a third Kelvin terminal relay pattern (130) via a fourth Kelvin terminal relay pattern (128), the third Kelvin terminal relay pattern (130) is bonded to a second Kelvin terminal connection terminal (144), the Kelvin terminal of the SIC MOSFET12 (222) is bonded to the second Kelvin terminal connection terminal (144), The gate terminals of the SIC MOSFET7 (212), the SIC MOSFET8 (214), and the SIC MOSFET9 (216) are respectively bonded to the respective gate resistances fixed to the second gate relay auxiliary substrate (126 s), the gate terminals of the SIC MOSFET10 (218), the SIC MOSFET11 (220), and the SIC MOSFET12 (222) are respectively bonded to the respective gate resistances fixed to the second gate relay auxiliary substrate (126 s), and the second gate relay auxiliary substrate (126 s) is bonded to the second gate connection terminal (146).

Description

High-power SIC MOSFET SSC switch module utilizing auxiliary substrate Technical Field The invention relates to a high-power SIC MOSFET (silicon carbide metal oxide semiconductor field effect transistor) SSC (single-sided cooling) switch module using an auxiliary substrate, which belongs to the technical field of the switch module. Background As a background art related to the present invention, there is a plastic packaged SIC power module technology disclosed in chinese laid-open patent publication No. 117913060. The packaging structure of the technology comprises a double-sided copper-clad ceramic substrate, a lead frame, a SIC chip, a copper sheet with a silver film layer, a copper bonding wire, a plastic package shell and a radiator. The source electrode on the lower surface of the SIC chip is electrically connected with the copper layer of the substrate through the sintered silver layer. On the other hand, in order to effectively solve the bonding of the chip and the copper wire surface, the copper sheet with the silver film layer is connected to the upper surface of the SIC chip through silver sintering. Thus, the current transmission capability of the module is improved, achieving more excellent electrical characteristics and good stability and reliability. In order to enhance the binding force with the plastic package shell, the direct current terminal and the alternating current terminal of the lead frame are respectively provided with 3 welding points and a central screw hole, the welding points of the terminals are respectively of a bending structure, and each terminal is characterized in that two round holes and 4V-shaped grooves are formed in the upper surface and the lower surface of each terminal. However, this technology bonds a chip only through a silver-sintered copper sheet to improve current transmission capability, and thus there is a limit in transmitting a large current, and a heat dissipation area is limited. As another background related to the present invention, there is a SIC power module technology with low parasitic inductance disclosed in chinese laid-open patent publication No. 118431209. The technology relates to a packaging technology of a power module, wherein the SIC power module comprises a first substrate, a second substrate, a power chip, bonding wires, a third substrate, a driving terminal and a power terminal. The first substrate, the second substrate and the third substrate are continuously configured in a bottom-up lamination mode, the power chip and the driving terminal are fixedly arranged on the second substrate, the power chip is electrically connected with the second substrate through a bonding wire, the power circuit is formed in the power chip, and the driving terminal is electrically connected with the power chip through the bonding wire. The driving terminal and the power terminal are both two side parts electrically connected with the input end of the second substrate, the output end of the second substrate, which is electrically connected with the power terminal, is arranged in the power chip, and the input end and the output end of the second substrate, which is electrically connected with the power terminal, are both positioned in the power loop, so that the SIC power module has the characteristic of improving the stability of the SIC power module. However, in this technique, the electrical connection power supply terminal 7 is configured to be connected across the substrate of the SIC power module, there is a possibility that parasitic capacitance increases, and the structure in which the plurality of drive terminals 6 are dispersed around the module causes connection with an external circuit to become complicated, and furthermore, the area of the substrate on which the power chip is configured is limited, and there is a limitation in the heat dissipation area. [ Patent literature ] (Patent document 1) CN117913060A (Patent document 2) CN118431209a Disclosure of Invention First, the technical problem to be solved The invention provides a high-power SIC MOSFET SSC switch module using an auxiliary substrate, which increases the pattern of the SSC power switch module for transmitting high current and provides high-efficiency heat dissipation characteristics, and by applying the auxiliary substrate insulated from the SSC substrate, the influence caused by leakage current, parasitic voltage and the like is eliminated, thereby improving the high input impedance electrical characteristics of the grid terminal of the SIC MOSFET module, and the size of the high-power SIC MOSFET module can be miniaturized, so that the terminal led out to the outside can be configured along the single axis direction. (II) technical scheme The invention provides a high-power SIC MOSFET SSC switch module using an auxiliary substrate, which provides a pattern for transmitting high current, applies the auxiliary substrate insulated with the SSC substrate to improve the high input imped