CN-121985579-A - Semiconductor element stacking structure

Abstract

The invention discloses a semiconductor element stacking structure, which comprises a plurality of first semiconductor element structures which are stacked and arranged. Each first semiconductor element structure comprises a substrate, a plurality of semiconductor elements, a rewiring layer, a first substrate through hole and a plurality of second substrate through holes. The substrate includes a front surface and a back surface. The plurality of semiconductor elements are located on the front surface of the substrate. The redistribution layer is located on the back side of the substrate. The first substrate is perforated through the substrate. The first substrate via is electrically connected to the redistribution layer. The second substrate is perforated through the substrate. Each second substrate through hole is positioned right below the corresponding semiconductor element. Each second substrate through hole is electrically connected with the corresponding semiconductor element and the rewiring layer. The size of the first substrate through hole is larger than that of each second substrate through hole.

Inventors

• ZHANG SHOUREN
• LV JUNLIN
• Ge Yongnian

Assignees

• 力晶积成电子制造股份有限公司

Dates

Publication Date

20260505

Application Date

20241119

Priority Date

20241029

Claims (20)

1. 1. A semiconductor element stack structure, comprising: a plurality of first semiconductor element structures arranged in a stacked manner, wherein each of the first semiconductor element structures comprises: A substrate comprising a front side and a back side; a plurality of semiconductor elements located on the front surface of the substrate; A rewiring layer on the back surface of the substrate; a first substrate penetrating through the substrate and electrically connected to the re-wiring layer, and A plurality of second substrate vias penetrating through the substrate, wherein each second substrate via is located directly below a corresponding semiconductor element and electrically connected to the corresponding semiconductor element and the redistribution layer, wherein The size of the first substrate penetration hole is larger than that of each second substrate penetration hole.
2. 2. The semiconductor device stack structure of claim 1, wherein the plurality of first semiconductor device structures comprises a plurality of semiconductor wafers.
3. 3. The semiconductor element stack structure of claim 1, wherein a plurality of the first semiconductor element structures comprise a plurality of semiconductor chips.
4. 4. The semiconductor device stack structure of claim 1, wherein the first substrate via is not located directly under a plurality of the semiconductor devices.
5. 5. The semiconductor device stack structure of claim 1, wherein an overall height of the first substrate via is greater than an overall height of each of the second substrate vias.
6. 6. The semiconductor device stack structure of claim 1, wherein a volume of the first substrate via is greater than a volume of each of the second substrate vias.
7. 7. The semiconductor device stack structure of claim 1, wherein a volume of the first substrate via is 10 times to 1000 times a volume of each of the second substrate vias.
8. 8. The semiconductor element stack structure of claim 1, wherein each of the first semiconductor element structures further comprises: a dielectric structure on the front side of the substrate, wherein a plurality of the semiconductor elements are located in the dielectric structure.
9. 9. The semiconductor device stack structure of claim 8, wherein the first substrate via extends into the dielectric structure.
10. 10. The semiconductor element stack structure of claim 1, wherein each of the first semiconductor element structures further comprises: A dielectric structure on the back side of the substrate, wherein the redistribution layer is located in the dielectric structure.
11. 11. The semiconductor device stack structure of claim 10, wherein the first substrate via and the plurality of second substrate vias extend into the dielectric structure.
12. 12. The semiconductor element stack structure of claim 1, wherein adjacent two of the first semiconductor element structures are bonded to each other.
13. 13. The semiconductor element stack structure according to claim 12, wherein the bonding method of adjacent two of the first semiconductor element structures includes a bump bonding method.
14. 14. The semiconductor element stack structure of claim 12, wherein the bonding method of adjacent two of the first semiconductor element structures comprises a hybrid bonding (hybrid bonding) method.
15. 15. The semiconductor device stack structure of claim 1, comprising a plurality of said first substrate vias and a plurality of said redistribution layers, wherein each of said first substrate vias is electrically connected to a corresponding one of said redistribution layers.
16. 16. The semiconductor device stack structure of claim 15, wherein a plurality of the first substrate vias are located between a plurality of the second substrate vias.
17. 17. The semiconductor element stack structure according to claim 1, further comprising: and a second semiconductor element structure, wherein a plurality of the first semiconductor element structures are stacked on the second semiconductor element structure.
18. 18. The semiconductor device stack structure of claim 17, wherein the second semiconductor device structure comprises a semiconductor wafer.
19. 19. The semiconductor element stack structure of claim 17, wherein the second semiconductor element structure comprises a semiconductor chip.
20. 20. The semiconductor element stack structure of claim 17, wherein one of the plurality of first semiconductor element structures that is closest to the second semiconductor element structure is bonded to the second semiconductor element structure.

Description

Semiconductor element stacking structure Technical Field The present invention relates to a semiconductor structure, and more particularly, to a semiconductor device stack structure. Background Currently, in a wafer stacking structure or a chip stacking structure, the number of wiring (routing) layers on the front surface of a substrate is increasing, so that the complexity of circuit design is increased. In addition, in the wafer stack structure or the chip stack structure, power and/or signal transmission is often performed through a through-substrate via (TSV). Therefore, how to reduce the occupied area (footprint) of the substrate via is a goal of continuous efforts. Disclosure of Invention The invention provides a semiconductor element stacking structure which can reduce the number of winding layers on the front surface of a substrate and the occupied area of substrate perforation. The invention provides a semiconductor element stacking structure, which comprises a plurality of first semiconductor element structures which are stacked and arranged. Each first semiconductor device structure includes a substrate, a plurality of semiconductor devices, a redistribution layer (redistribution layer, RDL), a first substrate via and a plurality of second substrate vias. The substrate includes a front surface and a back surface. The plurality of semiconductor elements are located on the front surface of the substrate. The redistribution layer is located on the back side of the substrate. The first substrate is perforated through the substrate. The first substrate via is electrically connected to the redistribution layer. The second substrate is perforated through the substrate. Each second substrate through hole is positioned right below the corresponding semiconductor element. Each second substrate through hole is electrically connected with the corresponding semiconductor element and the rewiring layer. The size of the first substrate through hole is larger than that of each second substrate through hole. In an embodiment of the invention, in the semiconductor device stacking structure, the plurality of first semiconductor device structures may be a plurality of semiconductor wafers. In an embodiment of the present invention, in the semiconductor device stacking structure, the plurality of first semiconductor device structures may be a plurality of semiconductor chips. In an embodiment of the invention, in the semiconductor device stacking structure, the first substrate through hole is not located directly under the plurality of semiconductor devices. In an embodiment of the present invention, in the semiconductor device stacking structure, an overall height of the first substrate via may be greater than an overall height of each of the second substrate vias. In an embodiment of the present invention, in the semiconductor device stacking structure, a volume of the first substrate through hole may be greater than a volume of each of the second substrate through holes. In an embodiment of the present invention, in the semiconductor device stacking structure, a volume of the first through-substrate via may be 10 times to 1000 times a volume of each of the second through-substrate vias. In an embodiment of the present invention, in the semiconductor device stack structure, each of the first semiconductor device structures may further include a dielectric structure. The dielectric structure is located on the front surface of the substrate. The plurality of semiconductor elements are located in the dielectric structure. In an embodiment of the invention, in the semiconductor device stack structure, the first substrate via may extend into the dielectric structure. In an embodiment of the present invention, in the semiconductor device stack structure, each of the first semiconductor device structures may further include a dielectric structure. The dielectric structure is located on the back side of the substrate. The rewiring layer is located in the dielectric structure. In an embodiment of the invention, in the semiconductor device stack structure, the first substrate via and the plurality of second substrate vias may extend into the dielectric structure. According to an embodiment of the present invention, in the semiconductor device stacking structure, two adjacent first semiconductor device structures may be bonded to each other. In an embodiment of the invention, in the semiconductor device stacking structure, a bonding method of two adjacent first semiconductor device structures may be a bump bonding (bump bonding) method. In an embodiment of the present invention, in the semiconductor device stacking structure, a bonding method of two adjacent first semiconductor device structures may be a hybrid bonding (hybrid bonding) method. According to an embodiment of the invention, the semiconductor device stack structure may include a plurality of first substrate vias and a plurality of redistribution layers. Each firs