CN-121985580-A - Method for manufacturing monolithic integrated circuits based on gallium nitride, for example, and corresponding integrated circuit

CN121985580ACN 121985580 ACN121985580 ACN 121985580ACN-121985580-A

Abstract

The present disclosure relates to methods of manufacturing monolithic integrated circuits, such as gallium nitride-based, and corresponding integrated circuits. A method of manufacturing a monolithic integrated circuit is provided. An exemplary method includes forming a functional block within and on top of at least one wide bandgap semiconductor material deposited on a silicon substrate, forming mutually separated interconnects on top of the functional block, separating the functional block, and forming a conductive connection between the substrate and a contact pad located on a top surface of the interconnect associated with the functional block. The separation of the functional blocks and the formation of the conductive connection are performed after the formation of the mutually separated interconnect portions.

Inventors

V. Volant
Curtin D.
P. ARNOLD

Assignees

意法半导体国际公司

Dates

Publication Date: 20260505
Application Date: 20251030
Priority Date: 20241031

Claims (12)

1. A method of manufacturing a monolithic integrated circuit comprising forming a functional block within and on top of at least one wide bandgap semiconductor material arranged on a silicon substrate, forming mutually separated interconnects on top of the functional block, separating the functional block, and forming a conductive connection between the silicon substrate and a contact pad, said contact pad being located on top of the interconnect associated with the functional block, in which method said separating of the functional block and said forming of the conductive connection are performed after said forming of the mutually separated interconnects; wherein said forming of the conductive connection comprises: A first deep trench is made alongside the contact pad and extending from the top surface of the interconnect portion up to the silicon substrate, Forming a conductive layer lining the bottom of the first deep trench and the sidewalls of the first deep trench in contact with the silicon substrate and extending on the top surface of the interconnect portion up to the contact pad, and Wherein forming two separate interconnects on top of two adjacent functional blocks comprises forming an initial trench between the two separate interconnects, and the separating comprises: -forming an additional trench between said two adjacent functional blocks such that an initial trench extends and extends through said at least one wide bandgap semiconductor material up to the silicon substrate, the initial trench and the additional trench forming a second deep trench, and -Forming an electrically insulating layer on the bottom of the second deep trench and on the top of the sidewalls.
2. The method of claim 1, wherein the conductive layer is formed on walls of the first and second deep trenches and on top surfaces of the two separate interconnects; Wherein the first portion of the conductive layer is removed from the second deep trench such that a portion of the sidewalls and bottom of the second deep trench are uncovered and a second portion of the conductive layer is left over the remaining portion of the sidewalls and bottom of the second deep trench, and Wherein the electrically insulating layer is formed to cover the electrically conductive layer except for the region on top of the one or more contact pads and to cover the uncovered portions of the sidewalls and bottom of the second deep trench.
3. The method of claim 2, further comprising forming connection balls on top of one or more portions of the conductive layer that are located on top of the contact pads.
4. The method of claim 1, wherein the monolithically integrated circuits are fabricated simultaneously with one or more other monolithically integrated circuits on the semiconductor wafer in locations separated by dicing lines, and separation trenches are created along these dicing lines and simultaneously with the formation of the first and second deep trenches, extending through the at least one wide bandgap semiconductor material as far as the silicon substrate, prior to sawing the semiconductor wafer along the dicing lines.
5. The method of claim 1, wherein the at least one wide bandgap semiconductor material is selected from the group consisting of gallium nitride and alloys thereof, and silicon carbide and alloys thereof.
6. A monolithic integrated circuit, comprising: a plurality of functional blocks located within and on top of the at least one wide bandgap semiconductor material disposed on the silicon substrate; An interconnect portion on top of each of the plurality of functional blocks, comprising a plurality of metal levels, a last metal level being partially covered by a passivation layer forming a top surface of the interconnect portion and having openings defining contact pads on the last metal level; A conductive connection between the contact pad and the silicon substrate, and Means for separating the plurality of functional blocks: Wherein the conductive connection comprises a first deep trench extending from the top surface of the interconnect portion to the silicon substrate and having no passivation layer, and Wherein the means for separating the plurality of functional blocks comprises a second deep trench located between two adjacent functional blocks, the second deep trench extending through the at least one wide bandgap semiconductor material between two interconnect portions associated with the two functional blocks as far as the silicon substrate, the second deep trench also not having a passivation layer.
7. The monolithic integrated circuit of claim 6, wherein first deep trench and second deep trench do not have a metal layer extending the last metal level.
8. The monolithic integrated circuit of claim 6, wherein The conductive connection comprises a conductive layer lining the bottom of the first deep trench and the sidewalls of the first deep trench in contact with the silicon substrate and extending on the top surface of the interconnect portion up to the contact pad, and -The means for separating the plurality of functional blocks comprises an electrically insulating layer located on the bottom of the second deep trench and on the top of the sidewalls.
9. The monolithic integrated circuit of claim 8, wherein a portion of the sidewalls and bottom of the second deep trench are covered by a portion of the conductive layer and the remaining portion of the sidewalls and bottom of the second deep trench are covered by an electrically insulating layer that also covers the remaining portion of the conductive layer except for the region located on top of the contact pad.
10. The monolithic integrated circuit of claim 9, further comprising connection balls on top of portions of the conductive layer that are on top of the contact pads.
11. The monolithic integrated circuit as recited in claim 6, wherein the at least one wide bandgap semiconductor material is selected from the group consisting of gallium nitride and alloys thereof, and silicon carbide and alloys thereof.
12. An integrated switching power supply device comprising the monolithic integrated circuit of claim 6.

Description

Method for manufacturing monolithic integrated circuits based on gallium nitride, for example, and corresponding integrated circuit Cross-reference to related application(s) The present application claims priority from french patent application FR2411941, entitled "PROCEDE DE FABRICATION D'UN CIRCUIT INTEGRE MONOLITHIQUE, PAR EXEMPLE A BASE DE NITRURE DE GALLIUM, ET CIRCUIT INTEGRE CORRESPONDANT", filed on 10/31 at 2024, which is incorporated herein by reference to the maximum extent allowed by law. Technical Field The present disclosure relates to integrated circuits, particularly monolithic integrated circuits and particularly those monolithic integrated circuits incorporating functional blocks produced on wide bandgap semiconductor materials (e.g., materials such as gallium nitride (GaN) and alloys thereof, or silicon carbide (SiC) and alloys thereof) located on silicon substrates, and examples of such materials are by no means exhaustive or limiting. For example, such functional blocks may together form an electronic device. Background When gallium nitride (GaN) and its alloys are used in such devices, such devices are simply referred to as GaN devices. When silicon carbide (SiC) and its alloys are used in such devices, such devices are simply referred to as SiC devices. One such electronic device is a switched mode power supply (DC-DC converter). In a switched mode power supply, the functional blocks may comprise: Transistors, typically High Electron Mobility Transistors (HEMTs), The drive is a drive device, which is provided with a drive, -And the like. Some of these HEMT transistors are high-side (HS) transistors, i.e., connected between the load and the supply voltage. The other HEMT transistors are Low Side (LS) transistors, i.e., connected between the load and ground. There are several integration possibilities for combining different functional blocks to form a GaN device or a SiC device. One example of this is discrete integration, where multiple discrete components are inserted into a package. Another example of this is monolithic integration, where the power supply, driving and other functions are designed into the same chip. In addition, wafer level chip scale packages (WL-CSP) in which the chip is not encapsulated in a package are of great interest because of their small footprint and small number of electrical connections, thereby reducing parasitic inductance, noise and leakage. The trend in the market for products based on wide bandgap materials (e.g., gallium nitride based materials) is directed to smaller and smaller packages with high performance characteristics such as high output current, low leakage, and high power consumption efficiency, which provides a solution to many problems. The first problem to be solved involves the physical separation of the layers of wide bandgap material. In fact, gallium nitride based power components are based, for example, on the structuring of gallium nitride layers deposited over the entire silicon wafer. But when the HS and LS transistors and the additional driver are combined on the same monolithic chip, these functional blocks need to be physically separated without any links between the low and high voltage (LS and HS) parts and between the HS and LS transistors and the driver. This physical separation is necessary to avoid leakage and breakdown voltage. The second problem to be solved relates to the polarization of the silicon substrate. In fact, when the electronic device is integrated into a system, the silicon substrate needs to be connected to ground or polarized to obtain acceptable device behavior by avoiding as much as possible the problems of leakage and noise affecting the performance of the device. In this regard, the silicon substrate must be polarized, e.g., connected to ground, and cannot be left floating because the threshold voltage of the GaN power device depends on the polarization of the silicon substrate. A third problem relates to the length of the electrical interconnect. In fact, the electrical interconnections inside the device must be kept as short as possible to avoid parasitic inductances and electromagnetic interference that cause power surges during power transistor switching. A fourth problem relates to the space taken up by the device, which needs to be as small as possible. The first and second problems mentioned above are solved or not present by means of discrete component integration. The third and fourth problems mentioned above remain problematic. To this end, a solution that moves to using monolithic components (i.e., components in which all functional blocks are formed within a single chip) is particularly advantageous. This makes it possible to solve the third and fourth problems mentioned above. But for all these monolithic solutions both the first and second problems mentioned above need to be solved at the chip level, since the wide bandgap material layer covers the whole surface of the chip. The fabric