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CN-121985581-A - Manufacturing method of SMT technology

CN121985581ACN 121985581 ACN121985581 ACN 121985581ACN-121985581-A

Abstract

The invention provides a manufacturing method of an SMT (surface mounting technology) process, which comprises the following steps of S1, providing a substrate to be subjected to the SMT process, wherein the substrate comprises a PMOS region and an NMOS region, a grid structure, a side wall and a first oxide layer covering the grid structure and the side wall are formed in the PMOS region and the NMOS region, S2, forming a tensile stress silicon nitride layer on the surface of the NMOS region, carrying out stress transmission, S3, forming a second oxide layer covering the PMOS region and the NMOS region, S4, removing the second oxide layer on the surface of the NMOS region, S5, removing the tensile stress silicon nitride layer on the surface of the NMOS region, and S6, integrally removing the residual first oxide layer and the residual second oxide layer. Through wholly depositing an oxide layer after removing the tensile stress silicon nitride layer of the PMOS region in the SMT process, the oxide layer loss of the PMOS region is compensated, the excessive risk of etching the side wall corners of the PMOS region in the process of removing the silicon nitride layer and the oxide layer is reduced on the premise of not increasing the cost of the photomask and not changing the core process by selective reservation and removal treatment, and the reliability of the device is improved.

Inventors

  • PENG AIDONG
  • HUANG QIANQIAN
  • ZHU KEBAO
  • FANG GUIQIN
  • LI YECHAO
  • HUANG RENDE

Assignees

  • 重庆芯联微电子有限公司

Dates

Publication Date
20260505
Application Date
20251219

Claims (9)

  1. 1. A method of manufacturing an SMT process comprising the steps of: S1, providing a substrate to be subjected to an SMT process, wherein the substrate comprises a PMOS region and an NMOS region, wherein a grid structure and a side wall and a first oxide layer covering the grid structure and the side wall are formed in the PMOS region and the NMOS region; S2, forming a tensile stress silicon nitride layer on the surface of the NMOS region, and carrying out stress transmission; S3, forming a second oxide layer covering the PMOS region and the NMOS region; S4, removing the second oxide layer on the surface of the NMOS region; s5, removing the tensile stress silicon nitride layer on the surface of the NMOS region; S6, removing the residual first oxide layer and the second oxide layer.
  2. 2. The method of claim 1, wherein forming a tensile silicon nitride layer on the surface of the NMOS region in step S2, and performing stress transfer comprises: s2.1, forming a tensile stress silicon nitride layer covering the PMOS region and the NMOS region on the surface of the first oxide layer; s2.2, removing the tensile stress silicon nitride layer on the surface of the PMOS region; s2.3, carrying out high-temperature annealing on the substrate, and applying the stress of the tensile stress silicon nitride layer to the NMOS region.
  3. 3. The method of claim 2, wherein the tensile stressed silicon nitride layer in step S2.1 is deposited using a CVD process.
  4. 4. The method of claim 2, wherein the high temperature anneal in step S2.3 is performed at a temperature of 1000 ℃ to 1300 ℃ using a spike anneal process.
  5. 5. The method according to claim 1, wherein the second oxide layer is formed in step S3 using a CVD process, in particular PECVD or ALDCVD.
  6. 6. The method of claim 1, wherein the second oxide layer thickness in step S3 is 50A-100A.
  7. 7. The method of claim 1, wherein removing the second oxide layer on the surface of the NMOS region in step S4 comprises: s4.1 spin-coating photoresist to form a photoresist layer covering the PMOS region and the NMOS region; s4.2, exposing and developing the photoresist layer to remove the photoresist on the surface of the NMOS region; And S4.3, removing the second oxide layer on the surface of the NMOS region by using a BOE solution.
  8. 8. The method of claim 7, wherein the spin-on photoresist step uses a negative photoresist, and the exposing step uses a mask for an SMT process.
  9. 9. The method of claim 1, wherein the removing of the tensile silicon nitride layer in step S5 is performed by a wet etching process, and the solution is a mixed solution of phosphoric acid and HF acid.

Description

Manufacturing method of SMT technology Technical Field The invention relates to the field of semiconductor manufacturing, in particular to a manufacturing method of an SMT process. Background In the field of semiconductor fabrication, stress Memorization Technology (SMT) is a critical strained silicon technology that increases the operating speed of N-type metal-oxide-semiconductor field effect transistors (NMOS) in process nodes of 90nm and below. The core principle is to apply tensile stress through the capping layer silicon nitride (SiN) to optimize carrier mobility of the NMOS. In this implementation, the silicon nitride layer in the P-type metal-oxide-semiconductor field effect transistor (PMOS) region needs to be removed by dry etching to avoid the tensile stress affecting the PMOS performance during stress transfer, but this process is accompanied by loss of the oxide layer (OX). After the SiN stress is transferred to the source drain and the gate by high temperature annealing, siN and OX in the NMOS region should be removed, and only the very thin OX remains in the PMOS region as a barrier layer, which makes the side wall corner of the region extremely prone to risk of overetching (undercut) (as shown in fig. 2). The above-mentioned excessive etching problem can seriously affect the structural integrity and electrical performance of the device, and becomes a key bottleneck for restricting the reliability of the SMT technology. How to reduce the risk of excessive etching of the PMOS region due to OX loss during the process of removing the NMOS region OX is a technical problem to be solved in the current process node semiconductor manufacture of 90nm and below. Disclosure of Invention In order to solve all or part of the problems in the prior art, the invention provides a manufacturing method of an SMT process, which is characterized in that an oxide layer is integrally deposited before a PMOS region tensile stress silicon nitride layer is removed in the SMT process, and the oxide layer is selectively reserved and removed, so that the loss of the PMOS oxide layer is compensated, the excessive risk of etching the corners of a side wall is reduced and the reliability of a device is improved on the premise of not increasing the cost of a photomask and not changing a core process. In order to achieve the above purpose, the present invention provides the following technical solutions: A method of manufacturing an SMT process comprising the steps of: S1, providing a substrate to be subjected to an SMT process, wherein the substrate comprises a PMOS region and an NMOS region, wherein a grid structure and a side wall and a first oxide layer covering the grid structure and the side wall are formed in the PMOS region and the NMOS region; S2, forming a tensile stress silicon nitride layer on the surface of the NMOS region, and carrying out stress transmission; S3, forming a second oxide layer covering the PMOS region and the NMOS region; S4, removing the second oxide layer on the surface of the NMOS region; s5, removing the tensile stress silicon nitride layer on the surface of the NMOS region; S6, removing the residual first oxide layer and the second oxide layer. In step S2, a tensile stress silicon nitride layer is formed on the surface of the NMOS region, and the process of performing stress transfer includes: s2.1, forming a tensile stress silicon nitride layer covering the PMOS region and the NMOS region on the surface of the first oxide layer; s2.2, removing the tensile stress silicon nitride layer on the surface of the PMOS region; s2.3, carrying out high-temperature annealing on the substrate, and applying the stress of the tensile stress silicon nitride layer to the NMOS region. The tensile stress silicon nitride layer in step S2.1 is deposited by a CVD process. The high temperature annealing temperature in the step S2.3 is 1000-1300 ℃, and a peak annealing process is adopted. The second oxide layer in step S3 is formed by CVD, specifically PECVD or ALDCVD. The thickness of the second oxide layer in the step S3 is 50A-100A. The removing the second oxide layer on the surface of the NMOS region in step S4 includes: s4.1 spin-coating photoresist to form a photoresist layer covering the PMOS region and the NMOS region; s4.2, exposing and developing the photoresist layer to remove the photoresist on the surface of the NMOS region; And S4.3, removing the second oxide layer on the surface of the NMOS region by using a BOE solution. The spin coating photoresist step uses negative photoresist, and the exposure step uses a photomask of an SMT process. And in the step S5, the tensile stress silicon nitride layer is removed by adopting a wet etching process, wherein the solution is a mixed solution of phosphoric acid and HF acid. Drawings In order to more clearly illustrate the technical solutions of specific embodiments of the present invention, the drawings that are needed in the description of the embodiments w