CN-121985582-A - Semiconductor structure and forming method thereof

CN121985582ACN 121985582 ACN121985582 ACN 121985582ACN-121985582-A

Abstract

A semiconductor structure is provided. The semiconductor structure includes a first source/drain feature over a first fin element, a second source/drain feature over a second fin element, and first and second gate stacks spanning the first and second fin elements. The semiconductor structure further includes a dielectric layer covering the second source/drain feature and the first source/drain feature, and an isolation feature interposed between the first source/drain feature and the second source/drain feature and between the first gate stack and the second gate stack. The semiconductor structure further includes a contact structure in the dielectric layer and electrically coupled to the first source/drain feature through the silicide layer. Embodiments of the present application also relate to semiconductor structures and methods of forming the same.

Inventors

You Jiaquan
XU ZHUYUAN
ZHANG JIAHAO
JIANG GUOCHENG
WANG ZHIHAO

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260505
Application Date: 20251229
Priority Date: 20250501

Claims (10)

1. A method for forming a semiconductor structure, comprising: forming a first active region and a second active region over a substrate; forming first and second source/drain features on the first and second active regions, respectively; forming a dielectric layer to cover the first source/drain feature and the second source/drain feature; Forming a gate stack across the first active region and the second active region; Patterning the dielectric layer to form an opening between the first source/drain feature and the second source/drain feature; Forming a spacer in the opening, and A contact structure is formed through the dielectric layer and over the first source/drain feature, wherein the contact structure has a conductivity greater than a conductivity of the first source/drain feature.
2. The method for forming the semiconductor structure of claim 1, wherein patterning the dielectric layer to form the opening comprises: forming a patterned mask layer over the dielectric layer and the gate stack, wherein the patterned mask layer has a trench pattern exposing the gate stack; Forming a protection member on the gate stack in the trench pattern, and The dielectric layer is etched.
3. The method for forming the semiconductor structure of claim 1, wherein the contact structure abuts the isolation feature.
4. The method for forming the semiconductor structure of claim 1 wherein the opening exposes a surface of the first source/drain feature and a surface of the second source/drain feature.
5. The method for forming the semiconductor structure of claim 1 wherein the first source/drain feature is merged with the second source/drain feature.
6. The method for forming the semiconductor structure of claim 1 wherein the first source/drain feature and the second source/drain feature are both doped with an n-type dopant.
7. The method for forming the semiconductor structure of claim 1 wherein the first source/drain feature is doped with an n-type dopant and the second source/drain feature is doped with a p-type dopant.
8. The method for forming the semiconductor structure of claim 1, further comprising: A gate spacer layer is formed along sidewalls of the gate stack, wherein the opening exposes sidewalls of the gate spacer layer.
9. A method for forming a semiconductor structure, comprising: forming a first active region and a second active region over a substrate; Forming an isolation structure between the first active region and a lower portion of the second active region; forming first and second source/drain features on the first and second active regions, respectively; Forming a contact etch stop layer to cover the first source/drain feature and the second source/drain feature, wherein a dielectric constant of the contact etch stop layer is higher than a dielectric constant of the isolation structure; Forming an interlayer dielectric layer over the contact etch stop layer; Forming a first gate stack and a second gate stack to surround the first active region and the second active region; forming an etch mask over the interlayer dielectric and the first and second gate stacks, wherein the etch mask includes a protection feature covering top surfaces of the first and second gate stacks; etching the interlayer dielectric layer, the contact etch stop layer, and at least one of the first source/drain feature and the second source/drain feature using the etch mask to form a first opening over the isolation structure, and A first spacer is formed in the first opening.
10. A semiconductor structure, comprising: a first source/drain feature over the first fin element; A second source/drain feature over the second fin element; A first gate stack and a second gate stack spanning the first fin element and the second fin element, wherein the first fin element and the second fin element extend longitudinally in a first direction and the first gate stack and the second gate stack extend longitudinally in a second direction different from the first direction, A dielectric layer covering the second source/drain feature and the first source/drain feature; an isolation feature interposed between the first source/drain feature and the second source/drain feature and between the first gate stack and the second gate stack, and A contact structure is located in the dielectric layer and electrically coupled to the first source/drain feature through a silicide layer, and the electrical conductivity of the silicide layer is between the electrical conductivity of the contact structure and the electrical conductivity of the first source/drain feature.

Description

Semiconductor structure and forming method thereof Technical Field Embodiments of the present application relate to semiconductor structures and methods of forming the same. Background The electronics industry is experiencing an increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low cost, high performance and low power Integrated Circuits (ICs). To date, these goals have been largely achieved by shrinking semiconductor IC dimensions (e.g., minimum component dimensions) and thereby improving production efficiency and reducing associated costs. However, such miniaturization introduces greater complexity into the semiconductor manufacturing process. Thus, achieving continued advances in semiconductor ICs and devices requires similar advances in semiconductor fabrication processes and techniques. Recently, multi-gate devices have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing Short Channel Effects (SCE). One such multi-gate device that has been introduced is a full-gate-all-around transistor (GAA). GAA devices are named for gate structures that can extend around the channel region and provide access to the channel on two or four sides. GAA devices are compatible with related Complementary Metal Oxide Semiconductor (CMOS) processes, and their structure allows them to shrink substantially while maintaining gate control and mitigating SCE. GAA devices provide channels in silicon nanowires/nanoplates. However, the fabrication of integrating GAA components around nanowires/nanoplatelets can be challenging. For example, while the current methods have been satisfactory in many respects, there is still a continuing need for improvement. Disclosure of Invention Some embodiments of the present application provide a method for forming a semiconductor structure comprising forming a first active region and a second active region over a substrate, forming a first source/drain feature and a second source/drain feature over the first active region and the second active region, respectively, forming a dielectric layer to cover the first source/drain feature and the second source/drain feature, forming a gate stack across the first active region and the second active region, patterning the dielectric layer to form an opening between the first source/drain feature and the second source/drain feature, forming an isolation feature in the opening, and forming a contact structure through the dielectric layer and over the first source/drain feature, wherein the contact structure has a conductivity greater than a conductivity of the first source/drain feature. Further embodiments of the present application provide a method for forming a semiconductor structure comprising forming a first active region and a second active region over a substrate, forming an isolation structure between lower portions of the first active region and the second active region, forming first source/drain features and second source/drain features over the first active region and the second active region, respectively, forming a contact etch stop layer to cover the first source/drain features and the second source/drain features, wherein a dielectric constant of the contact etch stop layer is higher than a dielectric constant of the isolation structure, forming an interlayer dielectric layer over the contact etch stop layer, forming first gate stack and second gate stack to surround the first active region and the second active region, forming an etch mask over the interlayer dielectric and the first gate stack and the second gate stack, wherein the etch mask comprises forming a protective layer over the first gate stack and the second gate stack, forming the first source/drain feature and the first etch stop layer in the first opening and the isolation structure. Still further embodiments of the present application provide a semiconductor structure comprising a first source/drain feature over a first fin element, a second source/drain feature over a second fin element, a first gate stack and a second gate stack across the first fin element and the second fin element, wherein the first fin element and the second fin element extend longitudinally in a first direction and the first gate stack and the second gate stack extend longitudinally in a second direction different from the first direction, a dielectric layer covering the second source/drain feature and the first source/drain feature, an isolation feature between the first source/drain feature and the second source/drain feature and between the first gate stack and the second gate stack, and a contact structure in the dielectric layer and electrically coupled to the first source/drain feature through a silicide layer