CN-121985583-A - Semiconductor device and method for forming the same

CN121985583ACN 121985583 ACN121985583 ACN 121985583ACN-121985583-A

Abstract

The present disclosure provides semiconductor devices and methods of forming the same. An exemplary method includes forming a superlattice structure above a substrate. The superlattice structure includes an upper portion separated from a lower portion by an insulating layer. The insulating layer comprises a crystalline metal oxide. The superlattice structure is patterned to form fins protruding from the substrate. A dummy gate stack is formed over a first portion of the fin. A second portion of the fin not covered by the dummy gate stack is recessed to form a source/drain trench. First source/drain features are formed in the source/source trenches and coupled to a lower portion of the superlattice structure. A second source/drain feature is formed in the source/drain trench and coupled to an upper portion of the superlattice. The dummy gate stack is replaced with a gate structure.

Inventors

LIN ZHIBIN
LIN ZHICHANG

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260505
Application Date: 20260109
Priority Date: 20250110

Claims (10)

1. A method of forming a semiconductor device, comprising the steps of: Forming a superlattice structure above a substrate, the superlattice structure including an upper portion separated from a lower portion by an insulating layer, wherein the insulating layer includes a crystalline metal oxide; patterning the superlattice structure to form a fin protruding from the substrate; forming a dummy gate stack over a first portion of the fin; Recessing a second portion of the fin not covered by the dummy gate stack to form a source/drain trench; Forming a first source/drain feature in the source/drain trench and coupled to the lower portion of the superlattice structure; Forming a second source/drain feature in the source/drain trench and coupled to the upper portion of the superlattice structure, and The dummy gate stack is replaced with a gate structure.
2. The method of claim 1, further comprising the step of: after forming the first source/drain features, forming a contact etch stop layer and an interlayer dielectric layer over the first source/drain features, Wherein the first source/drain feature and the second source/drain feature are separated by the contact etch stop layer and the interlayer dielectric layer.
3. The method of claim 1, wherein the lower portion of the superlattice structure comprises a first plurality of channel layers interleaved by a first plurality of sacrificial layers, and the upper portion of the superlattice structure comprises a second plurality of channel layers interleaved by a second plurality of sacrificial layers, and further comprising the steps of: after recessing the second portion of the fin, performing an etching process to selectively recess the first and second pluralities of sacrificial layers to form first and second pluralities of inner spacer grooves, respectively, and A first plurality of internal spacer features is formed in the first plurality of internal spacer grooves and a second plurality of internal spacer features is formed in the second plurality of internal spacer grooves.
4. A method of forming a semiconductor device, comprising the steps of: forming a first vertical stack of alternating channel layers and sacrificial layers over a substrate; depositing a dielectric layer over the first vertical stack; forming a second vertical stack of alternating channel layers and sacrificial layers over the dielectric layer; patterning the second vertical stack, the dielectric layer and the first vertical stack, thereby forming a fin structure over the substrate; Forming a trench extending through the fin structure; Performing a first etching process to selectively recess the plurality of sacrificial layers of the first vertical stack and the plurality of sacrificial layers of the second vertical stack, wherein an etchant of the first etching process etches the plurality of sacrificial layers at a first rate and etches the dielectric layer at a second rate less than the first rate; Performing a second etching process to selectively remove the remaining portions of the plurality of sacrificial layers of the first vertical stack and the remaining portions of the plurality of sacrificial layers of the second vertical stack, thereby forming a plurality of first gate openings and a plurality of second gate openings, respectively, and A first gate structure is formed in the first plurality of gate openings and a second gate structure is formed in the second plurality of gate openings.
5. The method of claim 4, wherein depositing the dielectric layer comprises performing an atomic layer deposition process and the dielectric layer comprises crystalline metal oxide.
6. The method of claim 4, further comprising the step of: Forming a first source/drain feature in the trench and coupled to the first vertically stacked plurality of channel layers; forming an isolation structure over the first source/drain feature, and A second source/drain feature is formed in the trench and coupled to the plurality of channel layers of the second vertical stack.
7. The method of claim 4, wherein the first etching process is performed to form a plurality of interior spacer recesses, and further comprising forming a plurality of interior spacer features in the plurality of interior spacer recesses, wherein the plurality of interior spacer features and the dielectric layer have different compositions.
8. A semiconductor device, comprising: A substrate; A lower source/drain feature disposed over the substrate; A first plurality of nanostructures coupled to the lower source/drain feature; A first gate structure surrounding each of the first plurality of nanostructures; an upper source/drain feature over the lower source/drain feature; a second plurality of nanostructures coupled to the upper source/drain features; A second gate structure surrounding each of the second plurality of nanostructures, and A dielectric layer providing isolation between the first gate structure and the second gate structure, wherein the dielectric layer comprises crystalline metal oxide.
9. The semiconductor element according to claim 8, further comprising: a contact etch stop layer and an interlayer dielectric layer are disposed between the lower source/drain feature and the upper source/drain feature.
10. The semiconductor element according to claim 8, further comprising: a plurality of internal spacers disposed between the first gate structure and the lower source/drain feature and between the second gate structure and the upper source/drain feature, Wherein the plurality of internal spacers and the dielectric layer have different compositions.

Description

Semiconductor device and method for forming the same Technical Field The present disclosure relates to a semiconductor device and a method of forming the same. Background The semiconductor integrated circuit (INTEGRATED CIRCUIT, IC) industry has experienced an exponential growth. Technological advances in IC materials and design have resulted in generation-to-generation ICs, each of which has smaller and more complex circuitry than the previous generation. During the evolution of ICs, functional density (i.e., the number of interconnected elements per die area) generally increases, while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) decreases. Such scaled down processes generally provide benefits by improving production efficiency and reducing associated costs. Such scaling also increases the complexity of processing and manufacturing ICs. For example, as integrated circuit (INTEGRATED CIRCUIT, IC) technology advances to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). A multi-gate element generally refers to an element having a gate structure or portion thereof disposed over more than one side of a channel region. fin-LIKE FIELD EFFECT transistor (FinFET) and gate-all-around (GAA) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. Finfets have elevated channels surrounded by gates on more than one side (e.g., the gate surrounds the top and sidewalls of a "fin" of semiconductor material extending from the substrate). The GAA transistor has a gate structure that may extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of the GAA transistor may be formed from nanowires, nanoplates, other nanostructures, and/or other suitable structures. The shape of the channel region is also given the alternative names of GAA transistors, such as nanoplate transistors or nanowire transistors. As the semiconductor industry further advances to sub-10 nanometer (nm) technology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges presented by manufacturing and design issues have led to stacked device structure configurations, such as complementary FIELD EFFECT transistors (C-FETs), in which n-type and p-type multi-gate transistors are vertically stacked one above the other. While existing methods of forming C-FETs are generally adequate, they are not satisfactory in all aspects. Disclosure of Invention According to one embodiment of the present disclosure, a method for forming a semiconductor device includes the following steps. A superlattice structure is formed above a substrate, the superlattice structure including an upper portion separated from a lower portion by an insulating layer, the insulating layer including a crystalline metal oxide. The superlattice structure is patterned to form fins protruding from the substrate. A dummy gate stack is formed over a first portion of the fin. A second portion of the fin not covered by the dummy gate stack is recessed to form a source/drain trench. A first source/drain feature is formed in the source/drain trench and coupled to a lower portion of the superlattice structure. A second source/drain feature is formed in the source/drain trench and coupled to an upper portion of the superlattice structure. And replacing the dummy gate stack with a gate structure. According to one embodiment of the present disclosure, a method for forming a semiconductor device includes the following steps. A first vertical stack of alternating channel layers and sacrificial layers is formed over a substrate. A dielectric layer is deposited over the first vertical stack. A second vertical stack of alternating channel layers and sacrificial layers is formed over the dielectric layer. The second vertical stack, the dielectric layer, and the first vertical stack are patterned, thereby forming a fin structure over the substrate. A trench is formed extending through the fin structure. A first etching process is performed to selectively recess the first vertically stacked sacrificial layer and the second vertically stacked sacrificial layer, an etchant of the first etching process etches the sacrificial layer at a first rate and etches the dielectric layer at a second rate that is less than the first rate. A second etching process is performed to selectively remove the plurality of remaining portions of the first vertically stacked sacrificial layer and the plurality of remaining portions of the second vertically stacked sacrificial layer, thereby forming a plurality of first gate openings and a plurality of second gate openings, respectively. And forming a first gate structure in the fir