CN-121985584-A - Stacked transistor, preparation method thereof, device and electronic equipment

CN121985584ACN 121985584 ACN121985584 ACN 121985584ACN-121985584-A

Abstract

The application provides a stacked transistor, a preparation method thereof, a device and electronic equipment, wherein the method comprises the steps of forming an active structure on a substrate; the method comprises the steps of forming a dummy gate stack structure on a substrate, wherein the dummy gate stack structure comprises a first dummy gate structure surrounding a first active structure, a gate isolation layer and a second dummy gate structure surrounding a second active structure, forming a first source drain epitaxy of a first transistor and a second source drain epitaxy of a second transistor, removing the first dummy gate structure and the second dummy gate structure, forming a through hole penetrating through the gate isolation layer, forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor, and forming a gate interconnection through hole in the through hole, wherein the gate interconnection through hole is connected with the first gate metal layer and the second gate metal layer respectively, and a first orthographic projection of the gate interconnection through hole in a first direction is located inside a second orthographic projection of the active structure in the first direction. By the application, parasitic capacitance can be reduced.

Inventors

WU HENG
JIANG JINGRU
CHEN YIFEI
WANG RUNSHENG
XU XIAOYAN
LI MING
HUANG RU

Assignees

北京大学

Dates

Publication Date: 20260505
Application Date: 20260112

Claims (10)

1. A method of fabricating a stacked transistor, comprising: Forming an active structure on a substrate, wherein the active structure comprises a first active structure and a second active structure which are sequentially stacked in a first direction; forming a dummy gate stack structure on the substrate, wherein the dummy gate stack structure comprises a first dummy gate structure surrounding the first active structure, a gate isolation layer and a second dummy gate structure surrounding the second active structure; forming a first source drain epitaxy of a first transistor and a second source drain epitaxy of a second transistor, wherein the second source drain epitaxy is formed after performing first rewinding on a wafer; Removing the first dummy gate structure and the second dummy gate structure, and forming a through hole penetrating through the gate isolation layer; The method comprises the steps of forming a second gate metal layer of a second transistor and a first gate metal layer of a first transistor, and forming a gate interconnection through hole in the through hole, wherein the gate interconnection through hole is respectively connected with the first gate metal layer and the second gate metal layer, a first orthographic projection of the gate interconnection through hole in the first direction is positioned inside a second orthographic projection of the active structure in the first direction, and the first gate metal layer is formed after second film reversing is performed on the wafer.
2. The method of claim 1, wherein forming the second gate metal layer of the second transistor and the first gate metal layer of the first transistor and forming a gate interconnect via in the through via comprises: Filling insulating materials in a first grid region corresponding to the first active structure and a first region of the through hole to form a first sacrificial layer, wherein the first region is a part of the through hole close to the first grid region; Filling conductive materials in a second gate region corresponding to the second active structure and a second region of the through hole to form a second gate metal layer and a first gate interconnection through hole of the second transistor, wherein the second region is a part of the through hole close to the second gate region; Performing a second rewinding; And removing the first sacrificial layer, filling conductive materials in the second gate region and the second region of the through hole to form a first gate metal layer and a second gate interconnection through hole of the first transistor, wherein the first gate interconnection through hole and the second gate interconnection through hole are connected and form a gate interconnection through hole.
3. The method of claim 1, wherein forming an active structure on a substrate comprises: Providing a substrate, and forming a laminated structure on the substrate, wherein the laminated structure comprises a first semiconductor layer, a second sacrificial layer and a second semiconductor layer which are stacked in the first direction; And etching the laminated structure to form the first active structure and the second active structure, wherein the etched second sacrificial layer is positioned between the first active structure and the second active structure.
4. The method of claim 3, wherein said removing the first dummy gate structure and the second dummy gate structure and forming a through hole through the gate spacer comprises: Removing the second dummy gate structure to expose the second gate region; removing the second sacrificial layer between the second gate region and the first gate region to form the through hole; And removing the first dummy gate structure to expose the first gate region.
5. The method of claim 1, wherein forming a first source drain extension of a first transistor and a second source drain extension of a second transistor comprises: etching the active structure to form a first source drain groove and a second source drain groove; filling insulating materials in the second source drain grooves to form third sacrificial layers; depositing a dielectric material on the third sacrificial layer to form a source-drain isolation layer; performing source-drain epitaxial growth in the first source-drain groove to form the first source-drain epitaxy; Performing first rewinding and thinning the substrate; removing the third sacrificial layer to expose the second source drain groove; And carrying out source-drain epitaxial growth in the second source-drain groove to form the second source-drain epitaxy.
6. The method of claim 1, wherein forming a dummy gate structure on the substrate comprises: depositing a semiconductor material with a preset height on the substrate to form the second pseudo gate structure; Depositing an insulating material on the second dummy gate structure to form the gate isolation layer; and depositing the semiconductor material on the gate isolation layer to form the first pseudo gate structure.
7. The method according to claim 1, wherein the method further comprises: forming a second back-end interconnect layer of the second transistor prior to the second rewinding; After forming the gate interconnect via, a first back-end interconnect layer of the first transistor is formed.
8. A stacked transistor prepared by the method of any of claims 1 to 7, the stacked transistor comprising: the first transistor comprises a first active structure and a first gate metal layer; A second transistor; the second transistor comprises a second active structure and a second gate metal layer; the first transistor and the second transistor are stacked in a first direction; The grid electrode interconnection through hole is electrically connected with the first grid metal layer and the second grid metal layer respectively, and orthographic projection of the grid electrode interconnection through hole in the first direction is located inside orthographic projection of the first active structure in the first direction.
9. A semiconductor device, comprising: a plurality of stacked transistors as claimed in claim 8; the stacked transistors are electrically connected through the back-end interconnection layer to form a functional circuit.
10. An electronic device, comprising: A circuit board; The semiconductor device of claim 9, wherein said semiconductor device is mounted to and electrically connected to said circuit board.

Description

Stacked transistor, preparation method thereof, device and electronic equipment Technical Field The present application relates to semiconductor manufacturing technology, and in particular, to a stacked transistor, a method for manufacturing the stacked transistor, a device, and an electronic apparatus. Background While moore's law is continually deepening, continuing to advance transistor scaling after the full round Gate (GAA) technology node is a hot spot problem that is currently being developed in the industry. Stacked transistors, through three-dimensional transistor stacking, can realize the integration of two or more layers of transistors in a vertical space, which helps to further increase the integration density of the transistors and improve the circuit performance, and is considered as one of important technologies for continuing the miniaturization of integrated circuits. How to achieve efficient metal interconnections and reduce parasitic capacitance in stacked transistors remains a current problem to be solved. Disclosure of Invention The embodiment of the application provides a stacked transistor, a preparation method thereof, a device and electronic equipment, which can realize grid interconnection in an active region so as to reduce parasitic capacitance. The technical scheme of the embodiment of the application is realized as follows: The embodiment of the application provides a preparation method of a stacked transistor, which comprises the steps of forming an active structure on a substrate, forming a pseudo gate stack structure on the substrate, forming a first pseudo gate structure, a gate isolation layer and a second pseudo gate structure, wherein the active structure comprises a first active structure and a second active structure which are sequentially stacked in a first direction, the pseudo gate stack structure comprises a first pseudo gate structure, a gate isolation layer and a second pseudo gate structure, the first pseudo gate structure surrounds the first active structure, the gate isolation layer surrounds the second active structure, a first source drain epitaxy and a second source drain epitaxy of the first transistor are formed, the second source drain epitaxy is formed after a wafer is subjected to first wafer rewinding, the first pseudo gate structure and the second pseudo gate structure are removed, a through hole penetrating through the gate isolation layer is formed, a second gate metal layer of the second transistor and the first gate metal layer of the first transistor are formed in the through hole, the first grid interconnection through hole is respectively connected with the first gate metal layer and the second gate metal layer, a first orthographic projection of the gate interconnection through hole in the first direction is located inside the active structure in the first direction, and the second orthographic projection of the first wafer is formed after the wafer is subjected to second wafer rewinding. In some possible embodiments, forming a second gate metal layer of the second transistor and a first gate metal layer of the first transistor and forming a gate interconnection via in the through hole includes filling insulating material in a first gate region corresponding to the first active structure and a first region of the through hole to form a first sacrificial layer, wherein the first region is a portion of the through hole near the first gate region, filling conductive material in a second gate region corresponding to the second active structure and a second region of the through hole to form a second gate metal layer of the second transistor and a first gate interconnection via, wherein the second region is a portion of the through hole near the second gate region, performing a second flip, removing the first sacrificial layer and filling conductive material in the second gate region of the second gate region and the through hole to form the first gate metal layer and the second gate interconnection via of the first transistor, and connecting the first gate interconnection via and the second gate interconnection via to form the gate interconnection via. In some possible embodiments, forming an active structure on a substrate includes providing a substrate and forming a stacked structure on the substrate, the stacked structure including a first semiconductor layer, a second sacrificial layer, and a second semiconductor layer stacked in a first direction, etching the stacked structure to form a first active structure and a second active structure, and the etched second sacrificial layer being located between the first active structure and the second active structure. In some possible embodiments, removing the first dummy gate structure and the second dummy gate structure and forming a through hole through the gate isolation layer includes removing the second dummy gate structure to expose the second gate region, removing the second sacrificial layer