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CN-121985585-A - Semiconductor structure and preparation method thereof

CN121985585ACN 121985585 ACN121985585 ACN 121985585ACN-121985585-A

Abstract

A semiconductor structure and a preparation method thereof are provided, wherein the preparation method comprises the steps of providing a substrate, comprising a first epitaxial layer, wherein the substrate comprises a diode area for forming a diode and a transistor area for forming a transistor, the diode comprises a first body area, the transistor comprises a second body area, a first photoresist layer is formed to cover the first epitaxial layer, patterning of the first photoresist layer and patterning for forming the first body area are formed by adopting the same mask plate, and adjusting injection is carried out by taking the first photoresist layer as a mask, a first included angle is formed between a first ion beam for adjusting injection and the normal direction of the surface of the substrate, so that the breakdown voltage of the diode is independently adjusted, and the ions for adjusting injection are blocked in the transistor area by the first photoresist layer. By tuning the implant to integrate the transistor and diode semiconductor structure, the reverse breakdown voltage of the diode is individually tuned without affecting other devices.

Inventors

  • YAO ZHIYUAN
  • FANG MINGXU
  • WANG LI
  • CHEN HUALUN

Assignees

  • 华虹半导体(无锡)有限公司
  • 上海华虹宏力半导体制造有限公司

Dates

Publication Date
20260505
Application Date
20260203

Claims (15)

  1. 1. A method of fabricating a semiconductor structure, comprising: providing a substrate comprising a first epitaxial layer, the substrate comprising a diode region for forming a diode comprising a first body region and a transistor region for forming a transistor comprising a second body region; Forming a first photoresist layer, wherein the first photoresist layer covers the first epitaxial layer, the first photoresist layer is subjected to patterning treatment, the patterned first photoresist layer comprises a first opening and a second opening, the first opening exposes the surface of the first body region, the second opening exposes the surface of the second body region, and the patterning of the first photoresist layer and the patterning of the first body region for forming the diode are manufactured by adopting the same mask plate; And adjusting the implantation by taking the first photoresist layer as a mask, wherein a first included angle is formed between the first ion beam for adjusting the implantation and the normal direction of the surface of the substrate, the first ion beam for adjusting the implantation is used for adjusting the breakdown voltage of the diode, and the ions for adjusting the implantation are blocked by the first photoresist layer in the transistor area.
  2. 2. The method of claim 1, wherein the first photoresist layer has a thickness of 3 μm to 4 μm.
  3. 3. The method of manufacturing according to claim 1, wherein the width of the first opening is 8 μm to 12 μm and the width of the second opening is 0.4 μm to 0.6 μm.
  4. 4. The method of manufacturing of claim 1, wherein the first body region of the diode comprises a first doped region and a second doped region, the first doped region and the second doped region being of opposite conductivity types; The ion implantation is regulated to enter the first doped region and is close to the position of the junction surface of the first doped region and the second doped region, and the concentration of the ion implantation is regulated to be 1E12 cm -3 to 5E12 cm -3 .
  5. 5. The method of manufacturing according to claim 1, wherein the first included angle ranges from 30 ° to 55 °.
  6. 6. The method of claim 1, wherein the adjusting implant ions are of the same or opposite conductivity type as the first doped region in the first body region.
  7. 7. The method of claim 6, wherein the dose ratio of the adjusted implant dose to the first body region is 1:10 to 1:20.
  8. 8. The method of claim 1, wherein the junction depth of the conditioning implant is 0.1 μm to 0.25 μm.
  9. 9. The method of claim 1, wherein the implantation is performed at an annealing temperature of 900 ℃ to 1100 ℃ for an annealing time of 5 seconds to 35 seconds.
  10. 10. The method of claim 1, wherein the transistor is an LDMOS, and the diode and the transistor are fabricated using BCD.
  11. 11. A semiconductor structure, comprising: A substrate including a first epitaxial layer, the substrate including a diode region for forming a diode including a first body region and a transistor region for forming a transistor including a second body region; Characterized by further comprising: And the interface adjusting region is formed in the first body region and is used for adjusting the doping concentration of the first body region.
  12. 12. The structure of claim 11 wherein the width of the first body region is 13 to 30 times the width of the second body region.
  13. 13. The structure of claim 11, wherein the doping concentration of the interface tuning region is a graded profile.
  14. 14. The structure of claim 11, wherein the interfacial adjustment region has a doping concentration of 1E12cm -3 to 5E12 cm -3 .
  15. 15. The structure of claim 11, wherein a ratio of a thickness of the interface modulation region to a thickness of the second type region is 1:10 to 1:20.

Description

Semiconductor structure and preparation method thereof Technical Field The invention relates to the field of semiconductors, in particular to a preparation method of a semiconductor device. Background A Zener diode (Z) is a common device in a semiconductor manufacturing process, which can maintain a constant voltage in a reverse breakdown state, and thus is widely used in the fields of a voltage stabilizing circuit, a voltage reference, overvoltage protection, signal clamping, and the like. When the BCD process platform integrates a device containing the zener diode, the inherent body region of the device and the heavily doped region with opposite conductivity type with the body region can be directly reused to construct and form the parasitic version-saving zener diode in order to simplify the preparation process and adapt to the target voltage condition. However, the gate driving voltage of the current BCD platform I/O device is 5V, which cannot meet the industry requirements of balancing gate oxide safety margin, voltage fluctuation tolerance and process implementation compatibility, and in order to make the breakdown voltage of the zener be in a region easy to regulate, the reverse breakdown voltage of the matched clamping zener needs to be increased to a driving voltage of 1.1 times, namely about 5.5V. When the BCD platform is integrated, the existing technology generally adopts a self-aligned technology to form a body region so as to improve the conduction characteristic of the transistor, and the on-state breakdown voltage of the transistor is enhanced by improving the doping concentration of the body region. However, because the BCD platform resistor and the transistor region both multiplex the process scheme of the logic platform, the process preparation parameters of the heavily doped region with opposite conductivity type to the body region cannot be adjusted independently, resulting in reduced reverse breakdown voltage of the formed diode, which is difficult to meet the application requirements in industry. Therefore, a preparation method compatible with the BCD platform process and capable of independently adjusting the reverse breakdown voltage of the diode is needed. Disclosure of Invention The invention adjusts the reverse breakdown voltage of the diode by adjusting and injecting the semiconductor structure of the integrated transistor and the diode, and does not affect other devices. In order to solve the problems, the invention provides a preparation method of a semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a first epitaxial layer, the substrate comprises a diode area and a transistor area, the diode area is used for forming a diode, the diode comprises a first body area, the transistor area is used for forming a transistor, the transistor comprises a second body area, a first photoresist layer is formed, the first photoresist layer covers the first epitaxial layer, the first photoresist layer is subjected to patterning treatment, the patterned first photoresist layer comprises a first opening and a second opening, the first opening exposes the surface of the first body area, the second opening exposes the surface of the second body area, the patterning of the first photoresist layer and the patterning of the first body area used for forming the diode are made of the same mask, the first photoresist layer is used as a mask for performing adjustment implantation, a first included angle is formed between a first ion beam used for adjusting the breakdown voltage of the diode and the first ion beam used for adjusting the breakdown voltage of the diode, and the first ion beam used for adjusting the breakdown voltage of the adjustment implantation is blocked by the photoresist layer in the first body area. The first photoresist layer has a thickness of 3 μm to 4 μm. The width of the first opening is 8 μm to 12 μm, and the width of the second opening is 0.4 μm to 0.6 μm. The first body region of the diode comprises a first doped region and a second doped region, the conductivity types of the first doped region and the second doped region are opposite, the ions injected in the adjusting mode enter the first doped region and are close to the position of the junction surface of the first doped region and the second doped region, and the concentration of the ions injected in the adjusting mode ranges from 1E12 cm -3 to 5E12 cm -3. The first included angle ranges from 30 ° to 55 °. The conductivity type of the implanted ions in the adjustment implantation is the same as or opposite to that of the first doped region in the first body region. The dose ratio of the adjusted implant to the first body region is 1:10 to 1:20. The junction depth of the accommodating implant is 0.1 μm to 0.25 μm. The annealing temperature of the implantation is adjusted to 900-1100 ℃ and the annealing time is 5-35 seconds. The transistor is an LDMOS, and the diode