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CN-121985586-A - Display panel and display device

CN121985586ACN 121985586 ACN121985586 ACN 121985586ACN-121985586-A

Abstract

The application discloses a display panel and a display device, wherein the display panel comprises a substrate, a thin film transistor layer and a shielding layer, the substrate is provided with a display area and a non-display area, the thin film transistor layer is arranged on the substrate and used for forming a grid driving circuit in the non-display area, the grid driving circuit comprises a plurality of shift registers, the shift registers comprise a plurality of thin film transistors, at least one of the thin film transistors is a target transistor, the thin film transistor layer comprises a first source-drain sub-layer, the first source-drain sub-layer is used for forming a first pole of the thin film transistor, the shielding layer is arranged between the thin film transistor layer and the substrate, the orthographic projection of the shielding layer on the substrate is a first projection area, the orthographic projection of the first source-drain sub-layer on the substrate is a second projection area, the orthographic projection of the second pole of the target transistor on the substrate is a third projection area, and at least part of the third projection area does not overlap with the first projection area and/or the second projection area.

Inventors

  • XU YUANJIE
  • XIE TAOFENG
  • XU GUANGHUA
  • WANG TAO
  • ZHANG DAIYING
  • WEI YULONG

Assignees

  • 京东方科技集团股份有限公司
  • 成都京东方光电科技有限公司

Dates

Publication Date
20260505
Application Date
20241031

Claims (17)

  1. 1. A display panel, the display panel comprising: A substrate base plate (10) having a display region (11) and a non-display region (12) located on one side of the display region (11); A thin film transistor layer (20) on the substrate (10) for forming a gate driving circuit (100) in the non-display region (12), the gate driving circuit (100) comprising a plurality of shift registers (110) in cascade, the shift registers (110) comprising a plurality of thin film transistors (111), at least one thin film transistor (111) of the plurality of thin film transistors (111) being a target transistor (112), the thin film transistor layer (20) comprising a first source drain sub-layer (21), the first source drain sub-layer (21) being for forming a first pole of the thin film transistor (111); and a shielding layer (30) between the thin film transistor layer (20) and the substrate (10), wherein the orthographic projection of the shielding layer (30) on the substrate (10) is a first projection area, the orthographic projection of the first source-drain sub-layer (21) on the substrate (10) is a second projection area, and the orthographic projection of the second pole of the target transistor (112) on the substrate (10) is a third projection area, and the third projection area is at least partially not overlapped with the first projection area and/or the second projection area.
  2. 2. The display panel according to claim 1, wherein the target transistor (112) includes a thin film transistor (111) having a largest aspect ratio among the plurality of thin film transistors (111).
  3. 3. The display panel according to claim 2, wherein the gate driving circuit (100) further comprises a square wave signal line (120), and the second pole of the target transistor (112) is connected to the square wave signal line (120).
  4. 4. A display panel according to any of claims 1-3, characterized in that the orthographic projection of the second pole of the target transistor (112) on the substrate base plate (10) does not at least partly overlap with the orthographic projection of the shielding layer (30) on the substrate base plate (10).
  5. 5. The display panel according to claim 4, characterized in that the orthographic projection of the second pole of the target transistor (112) on the substrate base plate (10) does not intersect the orthographic projection of the shielding layer (30) on the substrate base plate (10).
  6. 6. The display panel according to claim 4, characterized in that the orthographic projection of the first pole of the target transistor (112) on the substrate base plate (10) does not at least partly overlap with the orthographic projection of the shielding layer (30) on the substrate base plate (10).
  7. 7. The display panel according to claim 4, wherein each thin film transistor (111) of the plurality of thin film transistors (111) other than the target transistor (112) is a normal transistor (113), and wherein the orthographic projection of the shielding layer (30) on the substrate (10) includes orthographic projection of the normal transistor (113) on the substrate (10).
  8. 8. A display panel according to any one of claims 1-3, characterized in that the first source-drain sub-layer (21) is further used for forming an electrode transfer of the target transistor (112), the electrode transfer of the target transistor (112) being connected to the active layer of the same target transistor (112) through a communication hole; the thin film transistor layer (20) further includes: The second source-drain sub-layer (22) is positioned on one side of the first source-drain sub-layer (21) away from the substrate base plate (10), the second source-drain sub-layer (22) is used for forming a second pole of the target transistor (112), and the second pole of the target transistor (112) is connected with an electrode switching part of the same target transistor (112) through a communication hole.
  9. 9. The display panel according to claim 8, characterized in that the orthographic projection of the electrode transitions of the target transistors (112) on the substrate base (10) overlaps with the orthographic projection of the second poles of the same target transistors (112) on the substrate base (10).
  10. 10. The display panel according to claim 9, wherein both ends of the second pole of the target transistor (112) are respectively connected to the electrode transfer portion of the same target transistor (112) through communication holes, and the electrode transfer portions to which both ends of the second pole of the target transistor (112) are connected are different.
  11. 11. The display panel according to claim 10, characterized in that the orthographic projections of both ends of the second pole of the target transistor (112) on the substrate base plate (10) respectively comprise orthographic projections of the electrode transfer portions connected respectively on the substrate base plate (10).
  12. 12. The display panel according to claim 11, wherein the electrode transfer portion of the target transistor (112) is connected to the active layer of the same target transistor (112) through two communication holes.
  13. 13. The display panel according to claim 10, wherein the target transistor (112) has two second poles, each end of each second pole of the target transistor (112) being connected to an electrode transfer portion of the same target transistor (112) through a communication hole.
  14. 14. The display panel according to claim 8, wherein the thin film transistor layer (20) further comprises: a semiconductor sub-layer (23) located on a side of the first source-drain sub-layer (21) close to the substrate base plate (10), wherein the semiconductor sub-layer (23) is used for forming an active layer of the thin film transistor (111); And a gate sub-layer (24) located between the semiconductor sub-layer (23) and the first source-drain sub-layer (21), wherein the gate sub-layer (24) is used for forming a gate of the thin film transistor (111).
  15. 15. The display panel according to claim 8, wherein the gate driving circuit (100) further comprises a square wave signal line (120), the first source drain sub-layer (21) further forms the square wave signal line (120), and the gate sub-layer (24) further forms a signal transfer portion connected to the square wave signal line (120) and the second pole of the target transistor (112) through a communication hole, respectively.
  16. 16. The display panel according to claim 8, wherein each of the plurality of thin film transistors (111) except for the target transistor (112) is a normal transistor (113), the first source-drain sub-layer (21) is further used to form a second pole of the normal transistor (113), and the second pole of the normal transistor (113) is connected to an active layer of the same normal transistor (113) through a communication hole.
  17. 17. A display device comprising the display panel of claims 1-16.

Description

Display panel and display device Technical Field The application belongs to the technical field of display, and particularly relates to a display panel and a display device. Background At present, most of display panels adopt GOA (English: gate On Array, chinese: grid On Array substrate) to replace Gate IC (English: GATE INTEGRATED Circuit, chinese: grid driving chip) for display scanning driving, so that cost can be saved, process time can be shortened, and the effect of narrow frame can be realized. However, the display panel employed may have abnormal display problems caused by static electricity. If BSM (English: bottom SHELTER METAL, chinese: bottom shielding metal) is used to shield TFT (English: thin Film Transistor, chinese: thin film transistor) in GOA, electrostatic problem can be solved, but power consumption of GOA is increased. Disclosure of Invention The application provides a display panel and a display device, which aim to solve the problem of rising GOA power consumption at least to a certain extent. In a first aspect of the present application, there is provided a display panel including: A substrate base plate provided with a display area and a non-display area positioned at one side of the display area; The thin film transistor layer is positioned on the substrate base plate and used for forming a grid driving circuit in the non-display area; the grid driving circuit comprises a plurality of cascaded shift registers, wherein the shift registers comprise a plurality of thin film transistors, and at least one thin film transistor in the plurality of thin film transistors is a target transistor; The front projection of the shielding layer on the substrate is a first projection area, the front projection of the first source-drain sub-layer on the substrate is a second projection area, the front projection of the second pole of the target transistor on the substrate is a third projection area, and at least part of the third projection area does not overlap with the first projection area and/or the second projection area. In some embodiments, the target transistor comprises a thin film transistor of the plurality of thin film transistors having a largest aspect ratio. In some embodiments, the gate driving circuit further includes a square wave signal line, and the second pole of the target transistor is connected to the square wave signal line. In some embodiments, the orthographic projection of the second pole of the target transistor on the substrate base plate is at least partially non-overlapping with the orthographic projection of the shielding layer on the substrate base plate. In some embodiments, the orthographic projection of the second pole of the target transistor on the substrate does not intersect the orthographic projection of the shielding layer on the substrate. In some embodiments, the orthographic projection of the first pole of the target transistor on the substrate base plate is at least partially non-overlapping with the orthographic projection of the shielding layer on the substrate base plate. In some embodiments, each of the plurality of thin film transistors other than the target transistor is a common transistor, and the orthographic projection of the shielding layer on the substrate comprises orthographic projection of the common transistor on the substrate. In some embodiments, the first source-drain sub-layer is further used to form an electrode transfer portion of the target transistor, and the electrode transfer portion of the target transistor is connected to the active layer of the same target transistor through a communication hole; The thin film transistor layer further includes: The second source drain sub-layer is positioned on one side of the first source drain sub-layer far away from the substrate base plate and is used for forming a second pole of the target transistor, and the second pole of the target transistor is connected with an electrode switching part of the same target transistor through a communication hole. In some embodiments, an orthographic projection of an electrode landing of the target transistor on the substrate overlaps with an orthographic projection of a second pole of the same target transistor on the substrate. In some embodiments, both ends of the second pole of the target transistor are respectively connected with the electrode transfer portions of the same target transistor through communication holes, and the electrode transfer portions connected with both ends of the second pole of the target transistor are different. In some embodiments, the orthographic projections of both ends of the second pole of the target transistor on the substrate respectively include orthographic projections of the electrode transfer parts connected respectively on the substrate. In some embodiments, the electrode transfer portion of the target transistor is connected to the active layer of the same target transistor through two communication holes.