CN-121985587-A - Semiconductor device with more uniform thermal stress distribution on chip surface

CN121985587ACN 121985587 ACN121985587 ACN 121985587ACN-121985587-A

Abstract

The invention provides a semiconductor device with more uniform thermal stress distribution on the surface of a chip, which comprises a substrate of a first conductive type, wherein a plurality of rows of units are longitudinally arranged on the substrate, each row of units is transversely provided with a plurality of units, each unit is an active unit, a virtual unit or a virtual grid unit, the active units, the virtual units and the virtual grid units are arranged in any proportion in the transverse direction and the longitudinal direction, and the thermal stress on the surface of the semiconductor device is customized by adjusting the proportion of the active units, the virtual units and the virtual grid units in different areas or the length of a source area of the active units or the interval of the units or the mesa width of the units. The semiconductor device adopts a non-repetitive unit structure layout, and the temperature of the surface of the chip is adjusted according to the requirements of a designer by adjusting the unit layout or the unit structure, so that the thermal gradient of the surface of the chip can be reduced, the large thermal mechanical stress born by the semiconductor package can be lightened, and the service life and the reliability of the device and the interconnection structure of the device can be prolonged.

Inventors

Paula Diaz Regoza
Nick Schneider
Tommaso Steconi
Lars Noel Christian

Assignees

赛晶亚太半导体科技(浙江)有限公司
瑞士半导体科技有限公司

Dates

Publication Date: 20260505
Application Date: 20260408

Claims (10)

1. A semiconductor device having a more uniform thermal stress distribution across a chip surface, comprising: The semiconductor device comprises a substrate of a first conductivity type, wherein a plurality of rows of units are arranged on the substrate along the longitudinal direction, a plurality of units are arranged on each row along the transverse direction, the units are active units, virtual units or virtual grid units, the active units, the virtual units and the virtual grid units are arranged in any proportion in the transverse direction and the longitudinal direction, the plurality of rows of units on the semiconductor device are divided into a central area, a side area and a corner area through a groined shape, and the thermal stress of the surface of the semiconductor device is customized by adjusting the proportion of the active units, the virtual units and the virtual grid units in different areas or by adjusting the length of a source area of the active units in the different areas or by adjusting the interval of the units in the different areas or by adjusting the width of a table top of the units in the different areas.
2. The semiconductor device of claim 1, wherein the thermal stress distribution on the surface of the chip is more uniform, wherein: the active unit comprises two first grid grooves, a first body region of a second conductivity type, a first source region of a high doped first conductivity type, a first contact region and a first enhancement region of the first conductivity type, which are arranged in the substrate, wherein the first body region, the first source region and the first enhancement region are positioned between the two first grid grooves, the first source region is positioned above the first body region, the first enhancement region is positioned below the first body region, and the first contact region is used for connecting the first body region with a grid electrode; the dummy cell includes two first emitter trenches, a second body region of a second conductivity type, a second contact region, and a second enhancement region of the first conductivity type disposed in the substrate; the second body region and the second enhancement region are positioned between the two first emitter trenches, the second enhancement region is positioned below the second body region, the second contact region is used for connecting the second body region and the emitter, the first emitter trench is electrically isolated from other parts of the semiconductor device through the dielectric layer, and the first emitter trench is connected with the emitter contact; The virtual grid unit comprises two second grid grooves, a third body region of a second conductive type, a third contact region and a third enhancement region of a first conductive type, wherein the second grid grooves, the third body region, the third enhancement region and the third enhancement region are arranged in the substrate, the third enhancement region is arranged between the two second grid grooves, the third enhancement region is arranged below the third body region, the third contact region is used for connecting the third body region and a grid, the second grid grooves are electrically isolated from other parts of the semiconductor device through a dielectric layer, and the second grid grooves are connected with a grid contact.
3. The semiconductor device of claim 1, wherein the thermal stress distribution on the surface of the chip is more uniform, wherein: The active unit comprises two second emitter grooves, a third gate groove, a fourth body region of a second conductivity type, a second source region of a first conductivity type, a fourth contact region and a fourth enhancement region of the first conductivity type which are arranged in the substrate; the semiconductor device comprises a first emitter trench, a second emitter trench, a third gate trench, a fourth enhancement region, a fourth contact region, a dielectric layer, a third gate trench, a fourth enhancement region, a third gate trench, a fourth contact region and a third gate trench, wherein the first emitter trench is arranged between the first emitter trench and the first gate trench; The dummy cell includes three third emitter trenches, a fifth body region of the second conductivity type, a fifth contact region, and a fifth enhancement region of the first conductivity type disposed in the substrate; the semiconductor device comprises a fifth body region, a fifth enhancement region, a fifth contact region, a third emitter trench, a dielectric layer, a third emitter trench and a third emitter, wherein the fifth body region and the fifth enhancement region are positioned among three third emitter trenches; The virtual grid unit comprises two fourth emitter grooves, a fourth grid groove, a sixth body region, a sixth contact region and a sixth enhancement region, wherein the sixth body region, the fourth grid groove, the sixth contact region and the sixth enhancement region are arranged in the substrate, the sixth contact region and the sixth enhancement region are arranged between the two fourth emitter grooves, the sixth body region and the sixth enhancement region are arranged between the fourth emitter grooves and the fourth grid groove, the sixth enhancement region is arranged below the sixth body region, the sixth contact region is used for connecting the sixth body region and the grid, the fourth emitter grooves and the fourth grid groove are electrically isolated from other parts of the semiconductor device through a dielectric layer, the fourth grid groove is connected with the grid, and the fourth emitter grooves are connected with the emitters.
4. A semiconductor device according to claim 2 or 3, wherein the thermal stress distribution on the chip surface is more uniform, characterized in that: one side of the emitter trench or the gate trench is provided with an electrically floating second conductivity type highly doped region.
5. A semiconductor device according to claim 2 or 3, wherein the thermal stress distribution on the chip surface is more uniform, characterized in that: the proportion of active units in the central region < the proportion of active units in the side regions < the proportion of active units in the corner regions.
6. A semiconductor device according to claim 2 or 3, wherein the thermal stress distribution on the chip surface is more uniform, characterized in that: The length of the source region of the active cell in the center region < the length of the source region of the active cell in the side regions < the length of the source region of the active cell in the corner regions.
7. A semiconductor device according to claim 2 or 3, wherein the thermal stress distribution on the chip surface is more uniform, characterized in that: The pitch of the cells in the center region < the pitch of the cells in the side regions < the pitch of the cells in the corner regions.
8. A semiconductor device according to claim 2 or 3, wherein the thermal stress distribution on the chip surface is more uniform, characterized in that: The mesa width of the cells in the center region < the mesa width of the cells in the side regions < the mesa width of the cells in the corner regions.
9. A semiconductor device having a more uniform distribution of thermal stress on a surface of a chip according to claim 3, wherein: The proportion of the active units, the virtual units and the virtual grid units in each area is unchanged so as to maintain the proportion of the grid to the emitter, and more inactive units are formed by removing a contact area between part of emitter grooves or removing a contact area and a source area between part of emitter grooves and the grid grooves, so that the current density of the central part of the semiconductor device is reduced, and the thermal stress on the surface of the chip is uniformly distributed.
10. The semiconductor device of claim 2, wherein the thermal stress distribution on the surface of the chip is more uniform, wherein: the top of the grid electrode groove is provided with a first grid electrode of a heavily doped polysilicon layer, the polysilicon layer is partially interrupted in the area where the first contact areas of some active units are located, the polysilicon layer is not interrupted in the area where the first contact areas of some active units are located, the polysilicon layer is converted into an inactive unit by omitting the first source area, the top of the emitter groove is provided with a second grid electrode of the heavily doped polysilicon layer, the second grid electrode is interrupted with the first grid electrode along the longitudinal direction, and the thermal stress of the surface of the semiconductor device is customized by adjusting the proportion of the active units and the inactive units in different areas.

Description

Semiconductor device with more uniform thermal stress distribution on chip surface Technical Field The invention relates to the technical field of power semiconductors, in particular to a semiconductor device with more uniform thermal stress distribution on the surface of a chip. Background A semiconductor power device having a trench gate structure, such as a trench insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT for short) or a Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET for short. These devices have a gate contact that is electrically isolated from the rest of the transistor structure by a suitable dielectric material (e.g., silicon dioxide) that is used to control the device and switch it between an off state and an on state, or vice versa. Modern IGBT designs may contain many different design elements to achieve the desired performance of the device, such as cells that do not form Metal-Oxide-Semiconductor (MOS) channels (inactive cells), regions with floating p-type well layers, or additional trenches (dummy trenches) connected to the emitter potential. The dummy cells, active cells, and dummy gate cells may be laid out with or without floating p-well layers in order to provide electric field protection at the bottom of the gate trench and improve switching performance. These structures are typically repeated to form the active region of the semiconductor device. An IGBT semiconductor structure and a method for manufacturing the same are disclosed in chinese patent document CN117936573a, for example. However, for large area semiconductors, the thermal stress distribution on the chip surface may be very uneven, with temperature differences of up to tens of degrees. In fig. 1, a is a temperature gradient diagram of the chip surface in the prior art, and in fig. 1, curve a is a cross-sectional temperature gradient along a diagonal line. The average surface temperature of the emitter metallization on an IGBT chip is commonly referred to as the junction temperature, denoted Tj. Thermal stresses experienced by semiconductor devices during operation can lead to premature degradation of package interconnect structures (e.g., solder layers or bond wires) due to the presence of temperature gradients. Therefore, it is necessary to change the chip surface temperature distribution and reduce the temperature gradient. Disclosure of Invention The invention solves the technical problem of providing a semiconductor device with more uniform thermal stress distribution on the surface of a chip, which adopts a non-repetitive unit structure layout, adjusts the temperature of the surface of the chip according to the requirements of a designer by adjusting the unit layout or the unit structure, can reduce the thermal gradient of the surface of the chip, lighten the large thermal mechanical stress born by the semiconductor package, and prolongs the service life and the reliability of the device and an interconnection structure thereof. In order to solve the problems, the invention provides a semiconductor device with more uniform thermal stress distribution on the surface of a chip, which comprises a substrate of a first conductive type, wherein a plurality of rows of units are arranged on the substrate along the longitudinal direction, each row of units is provided with an active unit, a virtual unit or a virtual grid unit along the transverse direction, the active units, the virtual units and the virtual grid units are arranged in any proportion in the transverse direction and the longitudinal direction, the plurality of rows of units on the semiconductor device are divided into a central area, a side area and a corner area through a groined shape, and the thermal stress on the surface of the semiconductor device is customized by adjusting the proportion of the active units, the virtual units and the virtual grid units in different areas or by adjusting the length of source areas of the active units in the different areas or by adjusting the spacing of the units in the different areas or by adjusting the mesa width of the units in the different areas. Preferably, the active unit comprises two first grid trenches, a first body region of a second conductivity type, a first source region of a highly doped first conductivity type, a first contact region and a first enhancement region of the first conductivity type, which are arranged in the substrate, wherein the first body region, the first source region and the first enhancement region are positioned between the two first grid trenches, the first source region is positioned above the first body region, the first enhancement region is positioned below the first body region, and the first contact region is used for connecting the first body region with a grid electrode; the dummy cell includes two first emitter trenches, a second body region of a second conductivity type, a second contact region, and a second enhancement region of the f