CN-121985610-A - Twin self-calibration photoelectric probability bit circuit unit and preparation and use methods thereof

Abstract

The invention provides a twin self-calibration photoelectric probability bit circuit unit and a preparation and use method thereof, wherein the circuit unit comprises a self-calibration photoelectric differential module, a voltage comparator and a reference voltage source, the self-calibration photoelectric differential module is a pair of photoelectric indium gallium zinc oxide IGZO thin film transistors which are tightly coupled in space, the devices are patterned simultaneously through an ultraviolet lithography process and a radio frequency magnetron sputtering process, the atomic level matching of the reference tube and a photosensitive tube on the geometric dimension, the film thickness and the interface state density is ensured, only the difference exists on illumination conditions, common-mode interference such as aging caused by temperature drift and bias stress is effectively counteracted by utilizing the differential principle, a synchronous drift serial voltage division network is constructed by utilizing the physical characteristic of highly consistent aging trend, and the high-precision and high-stability in-situ photoelectric probability calculation is realized.

Inventors

• LIU FEI
• XIA CHENHAO
• CHEN WEICAN
• FU YUNYI
• ZHANG YUXIANG

Assignees

• 北京大学

Dates

Publication Date

20260505

Application Date

20251231

Claims (5)

1. 1. The self-calibration photoelectric differential module is characterized by comprising a pair of photoelectric Indium Gallium Zinc Oxide (IGZO) thin film transistors which are tightly coupled in space, wherein a first transistor T1 is a reference device, a second transistor T2 is a photosensitive device, and the two transistors have substantially consistent geometric dimensions and structures, and the specific structure is as follows: The source/drain electrodes are respectively positioned at two sides of the transistor channel, the electric control grid electrode is positioned between the source/drain electrodes and is arranged under the channel region and used for receiving an electric modulation signal to control the grid voltage of the channel, and the channels of two transistors in the differential pair are adjacent and parallel and share the same metal wire or are connected to the same bias voltage so as to ensure that the two transistors have the same electric working point; The gate oxide is located between the electrically controlled gate and the IGZO active layer, the IGZO active layer is deposited and patterned on the gate oxide, the active layer spans between the source/drain electrodes and is overlapped with the electrically controlled gate at the bottom in the vertical direction to form a conductive channel of the transistor, the protection layer covers the IGZO active layer and the exposed source/drain electrode surface, a metal shading layer is prepared on the upper layer of the protection layer, the shading layer completely covers the IGZO active layer and the channel region of the IGZO active layer in the vertical direction for the first transistor T1, an opening is formed in the T2 region of the shading layer for the second transistor T2, and a transparent protection layer is reserved above the channel of the T2.
2. 2. A method for preparing a twin self-calibration photoelectric probability bit circuit unit, which is characterized in that the method is based on a monolithic integration process to integrate the self-calibration photoelectric differential module as claimed in claim 1 into a circuit, and specifically comprises the following steps: The method comprises the steps of 1, device selection and layout design, wherein the specific method is to define that a first transistor T1 and a second transistor T2 have substantially consistent geometric dimensions and are spatially placed in a micron-sized close distance, a preset metal interconnection line in the layout design shorts a source electrode of the first transistor T1 and a drain electrode of the second transistor T2, and a preset metal interconnection line leads a source electrode and a drain electrode, an electric control grid electrode and the shorting node to be used for subsequent circuit connection; Step 2, cleaning a substrate and preparing an electric control grid, wherein the specific method comprises the steps of processing a target substrate by using a standard organic cleaning process, then depositing a metal layer serving as the electric control grid on the whole substrate, patterning the metal layer by using a photoetching method, and etching the redundant metal layer by using an etching method to form independent electric control grids of a patterned first transistor T1 and a patterned second transistor T2; depositing a grid oxide and an active layer, namely firstly growing the grid oxide by using atomic layer deposition, then adopting radio frequency magnetron sputtering to deposit an amorphous indium gallium zinc oxide film IGZO material as an active layer under the condition of not damaging vacuum, then patterning the active layer by using a photoetching method, and then removing redundant active layer materials by using an etching method to form a patterned active layer region; Step 4, source-drain electrode preparation and internal interconnection, namely, patterning a source-drain metal electrode region and a source-drain connecting line pattern between a first transistor T1 and a second transistor T2 by using a photoetching method, depositing a source-drain electrode layer, removing redundant metal materials by using a stripping mode to form a metal connecting line pattern between the patterned source-drain electrode region and the first transistor T1 and the second transistor T2, depositing metal to enable the patterned source-drain electrode region and the first transistor T1 and the second transistor T2 to be in reliable contact with an active layer, and simultaneously, directly and physically shorting a source electrode of the first transistor T1 and a drain electrode of the second transistor T2 in a chip according to a preset metal connecting line mode in layout design to enable the two transistors to form a series voltage division topology, wherein a shorting node is used as a common output end of the self-calibration photoelectric differential module; Step 5, preparing and annealing the protective layer, namely depositing the protective layer on the whole substrate, pre-running a plurality of metal precursor circulation before the formal growth of the protective layer starts, and accelerating the atomic arrangement of the device to reach a stable state in an annealing mode to form an oxide thin film transistor; The method comprises the steps of forming a light shielding layer on a first transistor T1 channel by patterning a light shielding layer area by using a photoetching mode, depositing opaque metal, removing redundant metal by using a stripping mode to form a patterned light shielding layer area, forming a light shielding layer for ensuring that the first transistor T1 is not influenced by external illumination, forming a photoelectric sensing window on a second transistor T2, forming a pressure welding hole by using a photoetching mode at a short circuit node between the first transistor T1 and the second transistor T2, forming a pressure welding hole by using a photoetching mode at a drain electrode of the first transistor T1 and a source electrode of the second transistor T2, and removing a protective layer above the pressure welding hole by using an etching mode to form a pressure welding hole window to finish the preparation of the micron-sized self-calibration photoelectric differential module; And 7, connecting the self-calibration photoelectric differential module into a PCB circuit system, wherein the self-calibration photoelectric differential module comprises a voltage comparator, a reference voltage source and a surrounding circuit, the specific method is that a chip-on-board packaging technology is adopted to electrically connect a pressure welding hole on the photoelectric differential module with a corresponding gold-plated bonding pad on the PCB, a short circuit node of a first transistor T1 and a short circuit node of a second transistor T2 are connected to a non-inverting input end of the voltage comparator, an inverting input end of the voltage comparator is connected to the reference voltage source, and an output end of the voltage comparator is used as a probability bit stream output end of the whole circuit.
3. 3. The method of claim 2, wherein the gate oxide material of step 3 is aluminum oxide, hafnium oxide or silicon dioxide, the protective layer of step 5 is 5-20 nm thick Al 2 O 3 , and is prepared by atomic layer deposition, and the light shielding layer of step 6 is aluminum Al or other opaque metal material with a thickness of more than 100nm, and is prepared by electron beam evaporation.
4. 4. The method of claim 2, wherein In the step 3, a ceramic target with a molar ratio of In to Ga to zn=1 to 1 is selected as the sputtering target, the background vacuum degree is better than 3×10 -4 Pa, the argon-oxygen ratio Ar to O 2 In the sputtering process is controlled to be 50:1-10:1, and the sputtering power is controlled to be 50 w-200 w.
5. 5. A method for generating photoelectric probability bits, which is used for a twin self-calibration photoelectric probability bit circuit unit prepared by the preparation method as claimed in claim 2, and specifically comprises the following steps: (1) Applying periodic power supply voltage pulse V DD to the self-calibration photoelectric probability bit circuit unit, for the first transistor, shorting the grid electrode of the first transistor to the power supply voltage pulse or applying a fixed bias pulse with the same amplitude as V DD to enable the first transistor to work in a conducting state during a pulse high level period to serve as an active load, for the second transistor, applying a control voltage signal V g to the grid electrode of the second transistor in a pulse mode, strictly limiting the amplitude of the grid control voltage pulse V g to be consistent with the amplitude of the power supply voltage pulse V DD , and simultaneously, grounding the source electrode of the second transistor so as to establish a dynamic working point based on a pulse series voltage division architecture between the two transistors; (2) For light modulation, a light intensity signal to be processed is directly projected to a photosensitive channel region of a second transistor, the light intensity change changes the concentration of photo-generated carriers in the channel and then changes the equivalent impedance of the second transistor, so that the direct current component of the voltage V node of the common output node of the self-calibration photoelectric differential module is deviated, the voltage is transmitted to the voltage comparator, when the instantaneous voltage V node containing noise is higher than the reference voltage V ref , a high level-logic '1' is output, and when the instantaneous voltage V node containing noise is lower than the reference voltage V ref , a low level-logic '0' is output, so that a continuous time discretized photo-random bit stream is generated; (3) For electric modulation, an electric signal to be processed is applied to the electric control gate V g of the second transistor in a pulse form, the electric field changes the carrier concentration in the channel, and further the equivalent impedance of the second transistor is changed, so that the direct current component of the voltage V node of the common output node of the self-calibration photoelectric differential module is offset, and the voltage is transmitted to the voltage comparator, so that a continuous time discretization random bit stream is generated.

Description

Twin self-calibration photoelectric probability bit circuit unit and preparation and use methods thereof Technical Field The invention belongs to the technical field of microelectronic devices and brain-like computing, and particularly relates to a twin self-calibration photoelectric probability bit circuit unit based on an oxide semiconductor Thin Film Transistor (TFT) and capable of in-situ counteracting electrical drift and performing optical signal perception, and a preparation method and a use method thereof. Background With the rapid development of internet of things (IoT) and edge computing technologies, artificial Intelligence (AI) hardware is facing a great demand for migration from the cloud to the edge. Under the trend, probability calculation (Probabilistic Computing) serves as a calculation paradigm inspired by the biological brain, and becomes a research hot spot in the later molar age due to the natural advantages of the calculation paradigm in tasks such as Bayesian reasoning, combined optimization problems (e.g. Ising model solving), generation type networks and the like. The basic unit of probability computation is a probability bit (p-bit) that is output as a random signal that fluctuates between 0 and 1, and the probability of output 1 can be non-linearly regulated by the input signal. In terms of hardware implementation, probability bit schemes based on Magnetic Tunnel Junctions (MTJs), resistive Random Access Memories (RRAMs), and Complementary Metal Oxide Semiconductors (CMOS) currently exist. Among them, an Indium Gallium Zinc Oxide (IGZO) Thin Film Transistor (TFT) -based photoelectric probability bit device is considered as an ideal carrier for constructing the next-generation brain-like visual perception system due to its integrated sensing characteristics, extremely low leakage current and good compatibility with back-end processes (BEOL). The device can directly modulate random bit stream by using the ambient light intensity, avoids frequent data handling between the sensor and the processor in the traditional architecture, and remarkably reduces power consumption and delay. However, although IGZO TFTs are excellent in photoelectric sensing and probability generation, they face a serious stability challenge in practical applications, which has become a key bottleneck restricting the technology from going to practical use. IGZO materials are amorphous oxide semiconductors in which there are a large number of metastable defects (such as oxygen vacancies and interface states) inside. Under long-term operating bias, light radiation, or thermal stress (i.e., positive bias temperature instability, PBTI), carriers can accumulate gradually in the trap level at the channel/dielectric interface, resulting in an irreversible shift in the threshold voltage (V th) of the device. This shift in threshold voltage is fatal to the probability calculation circuit. The activation function of the probability bits is extremely sensitive to the bias voltage. Once the device drifts, the center point of the Sigmoid curve shifts laterally over time. Without calibration, this can lead to the output probability deviating from a preset value (e.g., the state that would have output 50% probability might drift to 0% or 100%), resulting in the failure of the computational weights of the entire probabilistic neural network and even a complete breakdown of system function. To address this problem, existing solutions typically rely on external compensation mechanisms. For example, complex digital feedback circuits are used to monitor device state in real time through an analog-to-digital converter (ADC), and the amount of compensation is calculated using an algorithm, and then the gate voltage is dynamically adjusted through a digital-to-analog converter (DAC) to counteract drift. Although effective, the method introduces huge peripheral circuit overhead, obviously increases the chip area and the system power consumption, and the digital calibration process often needs to interrupt normal calculation tasks, so that the instantaneity is reduced. Another approach is to slow down drift by process improvements (e.g., dual active layers or special passivation), but this cannot fundamentally eliminate the effects of physical aging, and the increase in process complexity is counter to the initial goal of low cost fabrication. Therefore, it is needed to develop a circuit-level adaptive compensation scheme, which can realize in-situ and real-time automatic cancellation of device aging drift through simple hardware topology design on the premise of not depending on an external complex calibration circuit, so as to ensure the stability and reliability of the photoelectric probability bit under long-time working. Disclosure of Invention The invention aims to provide a twin self-calibration photoelectric probability bit circuit unit and a preparation method and a use method thereof. The photoelectric differential device with