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CN-121985612-A - Cascade multiplication linear mode silicon APD array chip and preparation method thereof

CN121985612ACN 121985612 ACN121985612 ACN 121985612ACN-121985612-A

Abstract

The invention belongs to the field of photoelectric technology, and discloses a cascade multiplication linear mode silicon APD array chip and a preparation method thereof, wherein the cascade multiplication linear mode silicon APD array chip comprises a substrate layer and a plurality of pixel structure units which are arranged on the substrate layer in an array manner; the substrate layer is made of P-doped gallium phosphide, the pixel structure unit comprises a P + buffer layer, an intrinsic absorption layer, a cascade multiplication layer and an n + contact layer which are sequentially arranged from bottom to top, and contact electrodes are respectively arranged on the top of the pixel structure unit and the substrate layer. The invention adopts the P-type gallium phosphide with wider forbidden bandwidth as the substrate, so that the silicon APD array chip provided by the invention can realize back light incidence and thinner silicon absorption layer design. The invention also adopts a cascade multiplication layer which is doped in a multistage periodic manner and is based on a relaxation space gain theory, so that the collision ionization coefficient of holes is restrained, the ionization coefficient ratio is reduced, and the gain of the silicon APD array pixels is improved.

Inventors

  • DENG JIE
  • CHEN JIAN
  • Wang Qiansan
  • DAI QIAN

Assignees

  • 西南技术物理研究所

Dates

Publication Date
20260505
Application Date
20260403

Claims (10)

  1. 1. A cascade multiplication linear mode silicon APD array chip comprises a substrate layer and a plurality of pixel structure units arranged on the substrate layer in an array manner, and is characterized in that, The substrate layer is made of P-type doped gallium phosphide; The pixel structure unit comprises a P + buffer layer, an intrinsic absorption layer, a cascade multiplication layer and an N + contact layer which are sequentially arranged from bottom to top, wherein the P + buffer layer is made of silicon or germanium silicon with the atomic fraction of 5% -20%, the doping source is boron or gallium, the intrinsic absorption layer is made of silicon or germanium silicon with the atomic fraction of 5% -20%, the cascade multiplication layer is provided with 2-10 stages of multiplication layers, each stage of multiplication layer comprises a first P-type charge layer, an intrinsic preheating layer, a second P-type charge layer, an intrinsic collision ionization layer and an N-type electric field reduction layer, the front j-1 stage multiplication layer further comprises an intrinsic relaxation layer positioned on the N-type electric field reduction layer, j represents the number of stages of the cascade multiplication layer, each layer of the cascade multiplication layer is made of silicon or germanium silicon with the atomic fraction of 5% -20%, the N + contact layer is made of silicon or germanium with the atomic fraction of 5% -20%, and the doping source is phosphorus or arsenic; and contact electrodes are respectively arranged on the top of the pixel structure unit and the substrate layer.
  2. 2. The cascade multiplication linear mode silicon APD array chip of claim 1, wherein the P-type doped gallium phosphide is a gallium phosphide single-crystal wafer with a crystal orientation of <100> or <111>, a doping source is beryllium, zinc or tellurium, a doping concentration is 1×10 18 ~3×10 19 cm -3 , and the thickness of the substrate layer is 100-500 μm.
  3. 3. The cascade multiplication linear mode silicon APD array chip according to claim 1, wherein the doping concentration of a doping source in the P + buffer layer material is 5 multiplied by 10 18 ~8×10 18 cm -3 , the thickness is 100-500 nm, the thickness of the intrinsic absorption layer is 1-80 μm, the doping concentration of a doping source in the N + contact layer material is 1 multiplied by 10 19 ~4×10 19 cm -3 , the thickness is 100-500 nm, and the P-type doping source in the cascade multiplication layer is boron or gallium, and the N-type doping source is phosphorus or arsenic.
  4. 4. The cascade multiplication linear mode silicon APD array chip according to claim 3, wherein for j cascade multiplication layers, in the 1 st-stage multiplication layer, the doping concentration of the first P-type charge layer is 8×10 17 ~9×10 17 cm -3 , the thickness is 10-40 nm, the thickness of the intrinsic pre-heating layer is 20-60 nm, the doping concentration of the second P-type charge layer is 6×10 17 ~1×10 18 cm -3 , the thickness is 10-20 nm, the thickness of the intrinsic collision ionization layer is 20-50 nm, the doping concentration of the N-type electric field reduction layer is 6×10 17 ~1×10 18 cm -3 , the thickness is 10-20 nm, and the thickness of the intrinsic relaxation layer is 80-100 nm; The 2 nd-j-1 st-order multiplication layer has the same structure, the doping concentration of the first P-type charge layer is 6 multiplied by 10 17 ~1×10 18 cm -3 , the thickness of the first P-type charge layer is 10-20 nm, the thickness of the intrinsic pre-heating layer is 20-60 nm, the doping concentration of the second P-type charge layer is 6 multiplied by 10 17 ~1×10 18 cm -3 , the thickness of the second P-type charge layer is 10-20 nm, the thickness of the intrinsic collision ionization layer is 20-50 nm, the doping concentration of the N-type electric field reduction layer is 6 multiplied by 10 17 ~1×10 18 cm -3 , the thickness of the first P-type charge layer is 10-20 nm, and the thickness of the intrinsic relaxation layer is 80-100 nm; In the j-th-stage multiplication layer, the doping concentration of the first P-type charge layer is 6 multiplied by 10 17 ~1×10 18 cm -3 , the thickness is 10-20 nm, the thickness of the intrinsic pre-heating layer is 20-60 nm, the doping concentration of the second P-type charge layer is 6 multiplied by 10 17 ~1×10 18 cm -3 , the thickness is 10-20 nm, the thickness of the intrinsic collision ionization layer is 20-50 nm, the doping concentration of the N-type electric field reduction layer is 1 multiplied by 10 18 ~2×10 18 cm -3 , and the thickness is 80-150 nm.
  5. 5. The cascade multiplication linear mode silicon APD array chip of claim 1, wherein an anti-reflection layer is arranged at the bottom of the substrate layer and opposite to the pixel structure unit, and the anti-reflection layer is a 145-155 nm silicon dioxide film.
  6. 6. The cascade multiplication linear mode silicon APD array chip of claim 5, wherein a mesa structure is arranged between the pixel structure unit and the substrate layer, passivation layers with protection function are arranged on side walls of the pixel structure unit and mesa isolation channels formed between adjacent pixel structure units, and the passivation layers comprise an in-situ passivation layer positioned on the inner side and a silicon nitride passivation layer positioned on the outer side.
  7. 7. A method for preparing a cascade multiplication linear mode silicon APD array chip, based on the chip of any one of claims 1 to 6, characterized by comprising the steps of: (1) Preparing a cascade multiplication APD epitaxial wafer; Sequentially epitaxially growing a p + buffer layer, an intrinsic absorption layer, a cascade multiplication layer and an n + contact layer on the substrate layer to obtain a cascade multiplication APD epitaxial wafer; (2) Preparing an APD array chip; Etching the cascade multiplication APD epitaxial wafer until the substrate layer forms an APD mesa to obtain a plurality of pixel structure units distributed on the substrate layer in an array mode, and preparing contact electrodes on the tops of the pixel structure units and the substrate layer to obtain the APD array chip.
  8. 8. The method of fabricating a cascade multiplication linear mode silicon APD array chip of claim 7, wherein step (1) comprises the sub-steps of: Sequentially epitaxially growing a p + buffer layer and an intrinsic absorption layer on the substrate layer by a low-pressure chemical vapor deposition method, wherein the epitaxial growth air pressure is 0.1-100 Pa, and the temperature is 500-800 ℃; Then sequentially epitaxially growing a periodically doped cascade multiplication layer and an n + contact layer on the intrinsic absorption layer by a molecular beam epitaxy method or an ultrahigh vacuum chemical vapor deposition method, wherein the epitaxial growth temperature is 500-800 ℃; step (2) comprises the following sub-steps: The silicon dioxide layer is evaporated by a plasma enhanced chemical vapor deposition method to be used as a mask, the photoresist is used as the mask, the silicon dioxide etching is carried out by adopting reactive ion etching, and after the pattern is transferred to the silicon dioxide, the photoresist is washed off by acetone; Contact electrodes are formed on the top of the picture element structural units and the bottom of the substrate layer by electron beam evaporation techniques.
  9. 9. The method for preparing the cascade multiplication linear mode silicon APD array chip, according to claim 8, is characterized in that passivation gas is adopted for in-situ passivation of an APD mesa obtained through etching to form an in-situ passivation layer, hydrofluoric acid solution is used for removing a residual silicon dioxide mask layer, deionized water is used for cleaning an epitaxial wafer, a silicon nitride passivation layer is formed on the surface of the in-situ passivation layer through a plasma enhanced chemical vapor deposition method, front electrode holes are formed through photoetching and hot phosphoric acid corrosion, and a side wall passivation layer is reserved.
  10. 10. The method for manufacturing a cascade multiplication linear mode silicon APD array chip according to claim 9, wherein the step (2) further comprises vapor deposition of an anti-reflection layer at a position opposite to the pixel structure unit at the bottom of the substrate layer by photolithography and magnetron sputtering.

Description

Cascade multiplication linear mode silicon APD array chip and preparation method thereof Technical Field The invention belongs to the technical field of photoelectricity, and relates to a cascade multiplication linear mode silicon APD array chip and a preparation method thereof. Background Avalanche multiplication refers to the formation of a high electric field region in the multiplication region of an avalanche photodiode (AVALANCHE PHOTODIODE, APD) under reverse bias voltage, where photo-generated electrons or holes are accelerated through the high electric field region and then collide with lattice atoms and ionize to generate new carriers, which can be accelerated to generate collision ionization, thereby increasing the number of carriers rapidly like an avalanche. APDs utilize this avalanche multiplication effect to multiply the photocurrent for high sensitivity detection. The linear mode APD operates below an avalanche breakdown voltage, which occurs the ratio of the photocurrent output by avalanche multiplication to the photocurrent without multiplication, referred to as the multiplication factor or gain. The electron impact ionization coefficient α of the silicon material is higher than the hole impact ionization coefficient β, and the ionization coefficient ratio k=β/α is relatively small, so that the conventional silicon APD cell device has a higher gain. The silicon APD cell device is generally manufactured by adopting an n +-p-π-p+ doping structure and adopting a planar process, and the voltage resistance value is improved by arranging an n + protection ring. However, the protection ring suppresses the intensity of avalanche multiplication electric field at the edge of the APD photosensitive region, so that the method is not suitable for preparing a silicon APD array chip with high-density pixels. For APD array chip fabrication, high density pixel and low crosstalk designs are typically required, for which silicon APD array chips are fabricated using mesa processes. On one hand, the elimination of the guard ring reduces the influence on the avalanche multiplication electric field, and on the other hand, the physical isolation of the table top can well inhibit the crosstalk of adjacent pixels. When the APD array chip is applied, the APD array chip needs to be interconnected with a readout circuit, namely, the front surface of the APD array chip is electrically connected with the readout circuit through back-off interconnection, so that an APD pixel incident light window needs to be designed on the back surface of the array chip. Because the APD back contact layer p + is a dead zone, it should be as thin as possible to avoid absorption of 500-1100 nm incident light. Meanwhile, the photo-sensitive surface of the APD array pixel is smaller, namely the transverse size of the APD is smaller, and the longitudinal size of the APD pixel is not larger than the transverse size in order to reduce the influence of the pixel edge electric field on the avalanche multiplication electric field and the like. For example, when the diameter of the photosensitive surface of the silicon APD array pixel is 20 mu m, the thickness of the silicon APD array chip is smaller than 20 mu m. Therefore, the technical difficulties are caused that on one hand, the ultra-thin chip thickness can lead to the chip technology not being carried out, and on the other hand, the ultra-thin chip thickness can lead to the gain reduction of the silicon APD pixels. Patent application cn201911093515.X discloses a cascaded avalanche multiplication photodiode, the first and second stage avalanches being formed from two independent lateral APD structures, respectively, the device structure being based on the n +-i-p-i-p+ doping profile of a silicon APD. The cascade avalanche multiplication photodiode structure utilizes the good passivation effect of the silicon surface thermal oxide layer to improve stability, and solves the problems of early breakdown, overlarge noise and gain saturation of the edge of the traditional punch-through avalanche multiplication photodiode APD. However, the cascade avalanche multiplication photodiode does not belong to a single APD pixel in the longitudinal direction, does not include an APD array arranged in high density, and the multiplication electric field of APDs is not periodically distributed. Patent application CN202410699586.9 discloses an avalanche photodetector with cascade multiplication effect, which adopts bulk silicon or SOI wafer, is based on normal incidence mesa APD device structure, is doped by ion implantation process, uses two or more sub multiplication regions with thinner thickness to replace the single multiplication region with thicker thickness in the prior art, forms a stepped avalanche multiplication electric field, mainly adopts a carrier-electron multiplication to reduce additional noise and improve the sensitivity of APD unit device. However, the avalanche photodetector is a normal inci