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CN-121985636-A - MicroLED display device based on epitaxial reconstruction and preparation method thereof

CN121985636ACN 121985636 ACN121985636 ACN 121985636ACN-121985636-A

Abstract

The invention discloses a MicroLED display device based on epitaxial reconstruction and a preparation method thereof, wherein the device comprises a plurality of groups of display units, each display unit is provided with three independent LED subunit structures which are vertically stacked, each subunit sequentially comprises an N-GaN layer, a selective light source layer, a SiN insulating layer and a P-GaN layer, and a high-resistance AlGaN layer is arranged between the subunits. Each subunit is provided with independent N-type and P-type sub-electrodes, the side walls of the N-type and P-type sub-electrodes are covered by an insulating layer, and all the sub-electrodes are coplanar with the upper surface of the top P-GaN layer. The selective light source layer is positioned between the projections of the corresponding sub-electrodes, and the length and width of the selective light source layer are smaller than 10 mu m. Each sub-electrode is connected to a separate contact electrode by a bonding layer and is electrically connected to an integrated CMOS driver. Through epitaxial reconstruction and stereoscopic integration, a high-density and independently addressable micron-sized pixel array is realized, and display brightness, color and energy efficiency are improved.

Inventors

  • FAN QIAN
  • NI XIANFENG
  • NAN QI

Assignees

  • 苏州汉骅半导体有限公司

Dates

Publication Date
20260505
Application Date
20251231

Claims (10)

  1. 1. A method for manufacturing a MicroLED display device based on epitaxial reconstruction, comprising the steps of: Forming a first part comprising the steps of: step 11, providing a silicon substrate, and sequentially epitaxially growing a nucleation layer and a buffer layer on the upper surface of the silicon substrate; Step 12, forming a first light emitting structure, including: step 121, epitaxially growing a first N-GaN layer on the upper surface of the buffer layer; step 122, growing a first SiN insulating layer on the first N-GaN layer by chemical vapor deposition; step 123, etching a part of the first SiN insulating layer to the upper surface of the first N-GaN layer to form a first groove; Step 124, epitaxially growing a first selective light source layer, wherein the first selective light source layer fills the first groove; step 125, flattening the upper surfaces of the first SiN insulating layer and the first selective light source layer, and epitaxially growing a first P-GaN layer; Step 13, epitaxially growing a first high-resistance AlGaN layer on the first P-GaN layer; Step 14, forming a second light emitting structure, including: step 141, epitaxially growing a second N-GaN layer on the upper surface of the first high-resistance AlGaN layer; step 142, growing a second SiN insulating layer on the second N-GaN layer by chemical vapor deposition; Step 143, etching a part of the second SiN insulating layer to the upper surface of the second N-GaN layer to form a second groove; Step 144, epitaxially growing a second selective light source layer, wherein the second selective light source layer fills the second groove; step 145, flattening the upper surfaces of the second SiN insulating layer and the second selective light source layer, and epitaxially growing a second P-GaN layer; step 15, epitaxially growing a second high-resistance AlGaN layer on the second P-GaN layer; step 16, forming a third light emitting structure, including: step 161, epitaxially growing a third N-GaN layer on the upper surface of the second high-resistance AlGaN layer; step 162, growing a third SiN insulating layer on the third N-GaN layer by chemical vapor deposition; step 163, etching a part of the third SiN insulating layer to the upper surface of the third N-GaN layer to form a third groove; Step 164, epitaxially growing a third selective light source layer, wherein the third selective light source layer fills the third groove, and the projection of the third selective light source layer on the first N-GaN layer and the projection of the second selective light source layer and the projection of the first selective light source layer on the first N-GaN layer are distributed at intervals; step 165, flattening the upper surfaces of the third SiN insulating layer and the third selective light source layer, and epitaxially growing a third P-GaN layer; step 17, forming an electrode structure, including: step 171, etching a part of each layer on the first N-GaN layer and a part of the first N-GaN layer along the thickness direction of the first component to form a first N-type sub-electrode groove; step 172, etching a part of each layer on the first P-GaN layer and a part of the first P-GaN layer along the thickness direction of the first component to form a first P-type sub-electrode groove; step 173, etching a part of each layer on the second N-GaN layer and a part of the second N-GaN layer along the thickness direction of the first component to form a second N-type sub-electrode groove; step 174, etching a part of each layer on the second P-GaN layer and a part of the second P-GaN layer along the thickness direction of the first component to form a second P-type sub-electrode groove; Step 175, etching a part of each layer on the third N-GaN layer and a part of the third N-GaN layer along the thickness direction of the first component to form a third N-type sub-electrode groove; Step 176, etching a part of the third P-GaN layer along the thickness direction of the first component to form a third P-type sub-electrode groove; Step 177, a first N-type sub-electrode, a first P-type sub-electrode, a second N-type sub-electrode, a second P-type sub-electrode, a third N-type sub-electrode, and a third P-type sub-electrode are arranged, and are respectively located in the first N-type sub-electrode groove, the first P-type sub-electrode groove, the second N-type sub-electrode groove, the second P-type sub-electrode groove, the third N-type sub-electrode groove, and the third P-type sub-electrode groove in a one-to-one correspondence manner; The projection of the first selective light source layer on the first N-GaN layer is positioned between the projections of the first N-type sub-electrode and the first P-type sub-electrode on the first N-GaN layer, the projection of the second selective light source layer on the first N-GaN layer is positioned between the projections of the second N-type sub-electrode and the second P-type sub-electrode on the first N-GaN layer, the projection of the third selective light source layer on the first N-GaN layer is positioned between the projections of the third N-type sub-electrode and the third P-type sub-electrode on the first N-GaN layer, and the length and the width of the first selective light source layer, the second selective light source layer and the second selective light source layer in the direction vertical to the thickness direction of the first component are smaller than 10 mu m; forming a second part comprising the steps of: step 21, providing a CMOS driver, forming a bonding layer above the CMOS driver; step 22, etching the bonding layer along the thickness direction of the second component to form six through holes penetrating through the bonding layer; Step 23, placing a first N-type contact electrode, a first P-type contact electrode, a second N-type contact electrode, a second P-type contact electrode, a third N-type contact electrode and a third P-type contact electrode in the through hole respectively; Bonding the first component and the second component, comprising the steps of: Step 31, transposing the second component, aligning and bonding the first N-type sub-electrode and the first N-type contact electrode, the first P-type sub-electrode and the first P-type contact electrode, the second N-type sub-electrode and the second N-type contact electrode, the second P-type sub-electrode and the second P-type contact electrode, the third N-type sub-electrode and the third N-type contact electrode, and the third P-type sub-electrode and the third P-type contact electrode, and forming a first N-electrode, a first P-electrode, a second N-electrode, a second P-electrode, a third N-electrode, and a third P-electrode respectively; And step 32, removing the silicon substrate, the nucleation layer and the buffer layer to obtain the MicroLED display device.
  2. 2. The method for manufacturing a MicroLED display device according to claim 1, wherein the first, second, and third selective light source layers are any one of a blue light source layer, a green light source layer, and a red light source layer and are not repeated.
  3. 3. The method for manufacturing a MicroLED display device according to claim 2, wherein the steps 122 to 124 are performed a plurality of times according to parameter settings to form a first selective light source layer of a target shape, the first selective light source layer having a cross-sectional shape in a thickness direction of the first member of one of a regular trapezoid, an inverted trapezoid, a diamond shape, and a hexagon shape, and/or, The steps 142-144 are performed a plurality of times to form a second selective light source layer of a target shape, the second selective light source layer having a cross-sectional shape in the thickness direction of the first member of one of a regular trapezoid, an inverted trapezoid, a diamond shape, and a hexagon shape, and/or, And performing the steps 162-164 for a plurality of times to form a third selective light source layer with a target shape, wherein the cross section shape of the third selective light source layer along the thickness direction of the first component is one of a regular trapezoid, an inverted trapezoid, a diamond shape and a hexagon shape.
  4. 4. The method of claim 1, wherein the step 123 further comprises growing a first passivation layer on sidewalls of the first recess, and/or, Step 143 further comprises growing a second passivation layer on sidewalls of the second recess and/or, Step 163 further comprises growing a third passivation layer on sidewalls of the third recess.
  5. 5. A MicroLED display device based on epitaxial reconstruction, comprising a plurality of groups of display cells, each of said display cells comprising: a first N-GaN layer; A first selective light source layer covering a portion of an upper surface of the first N-GaN layer; A first SiN insulating layer covering the upper surface of other parts of the first N-GaN layer and positioned on the periphery of the first selective light source layer; a first P-GaN layer covering the upper surfaces of the first selective light source layer and the first SiN insulating layer; A first high-resistance AlGaN layer covering the first P-GaN layer; A second N-GaN layer; a second selective light source layer covering a portion of an upper surface of the second N-GaN layer; a second SiN insulating layer covering the upper surface of other parts of the second N-GaN layer and positioned on the periphery of the second selective light source layer; a second P-GaN layer covering the upper surfaces of the second selective light source layer and the second SiN insulating layer; a second high-resistance AlGaN layer covering the second P-GaN layer; A third N-GaN layer; a third selective light source layer covering a portion of an upper surface of the third N-GaN layer; A third SiN insulating layer covering the upper surface of other parts of the third N-GaN layer and positioned on the periphery of the third selective light source layer; A third P-GaN layer covering the upper surfaces of the third selective light source layer and the third SiN insulating layer; The first N-type sub-electrode is connected in the first N-GaN layer and extends back to the first N-GaN layer; the first P-type sub-electrode is connected in the first P-GaN layer and extends back to the first N-GaN layer; the second N-type sub-electrode is connected in the second N-GaN layer and extends back to the first N-GaN layer; the second P-type sub-electrode is connected in the second P-GaN layer and extends back to the first N-GaN layer; a third N-type sub-electrode connected in the third N-GaN layer and extending away from the first N-GaN layer; a third P-type sub-electrode connected in the third P-GaN layer and extending away from the first N-GaN layer; The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer respectively cover the side walls of the first N-type sub-electrode, the first P-type sub-electrode, the second N-type sub-electrode, the second P-type sub-electrode, the third N-type sub-electrode and the third P-type sub-electrode in a one-to-one correspondence manner; the upper surfaces of the first N-type sub-electrode, the first P-type sub-electrode, the second N-type sub-electrode, the second P-type sub-electrode, the third N-type sub-electrode, the third P-type sub-electrode and the third P-GaN layer are positioned on the same reference plane; The projection of the first selective light source layer on the first N-GaN layer is positioned between the projections of the first N-type sub-electrode and the first P-type sub-electrode on the first N-GaN layer, the projection of the second selective light source layer on the first N-GaN layer is positioned between the projections of the second N-type sub-electrode and the second P-type sub-electrode on the first N-GaN layer, the projection of the third selective light source layer on the first N-GaN layer is positioned between the projections of the third N-type sub-electrode and the third P-type sub-electrode on the first N-GaN layer, and the length and the width of the first selective light source layer, the second selective light source layer and the third selective light source layer in the direction vertical to the thickness of the display device are smaller than 10 mu m; The bonding layer covers the third P-GaN layer and is provided with six through holes, a first N-type contact electrode, a first P-type contact electrode, a second N-type contact electrode, a second P-type contact electrode, a third N-type contact electrode and a third P-type contact electrode are respectively placed, the first N-type contact electrode and the first N-type sub-electrode form a first N electrode, the first P-type contact electrode and the first P-type sub-electrode form a first P electrode, the second N-type contact electrode and the second N-type sub-electrode form a second N electrode, the second P-type contact electrode and the second P-type sub-electrode form a second P electrode, the third N-type contact electrode and the third N-type sub-electrode form a third N electrode, and the third P-type contact electrode and the third P-type sub-electrode form a third P electrode; and the CMOS driver covers the upper surface of the bonding layer and is electrically connected with the first N electrode, the first P electrode, the second N electrode, the second P electrode, the third N electrode and the third P electrode.
  6. 6. The MicroLED display device according to claim 5, wherein the first, second, and third selective light source layers have lengths and widths in a direction perpendicular to a thickness direction of the display device of 0.1 μm to 2.5 μm.
  7. 7. The MicroLED display device according to claim 5, wherein the first, second, and third selective light source layers are different in shape and size.
  8. 8. The MicroLED display device according to claim 5, wherein the first, second, and third SiN insulating layers are light transmissive structures.
  9. 9. The MicroLED display device according to claim 5, wherein the first, second, and third N-GaN layers have a thickness of 1.5-10 μm.
  10. 10. The MicroLED display device according to claim 5, wherein the first, second, and third P-GaN layers are 200nm-2 μm thick.

Description

MicroLED display device based on epitaxial reconstruction and preparation method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a MicroLED display device based on epitaxial reconstruction and a preparation method thereof. Background MicroLED shows that the technology industrialization process is subject to the bottleneck of "mass transfer", which has seen great challenges in terms of efficiency, yield, cost and pixel miniaturization. For example, tens of millions or even hundreds of millions of micron-sized LED chips need to be accurately picked, placed and bonded to a driving backboard, the process is extremely complex, the speed is low, the yield is difficult to improve, and the method is a main cause of high cost. After transfer, the N-type and P-type electrodes and the driving circuit are required to be simultaneously bonded in a miniaturized and high-precision mode for each MicroLED pixels, and the requirements on alignment precision and process stability are extremely high. As pixel sizes shrink (< 10 μm), pick and place difficulties of conventional transfer techniques increase exponentially, limiting further improvements in display resolution and resolution (PPI). In the prior art, a scheme is adopted to epitaxially grow the whole wafer structure at one time, and then electrodes are etched and installed (as shown in fig. 1), so that the design space of a chip is limited on one hand, and the size of the chip cannot be small. On the other hand, the blue light emitting layer, the green light emitting layer, and the red light emitting layer become smaller gradually, and there is a problem in that the light emitting layers overlap in the vertical direction, and the light emitting efficiency is affected. Also, materials such as indium gallium phosphide are generally required for highly efficient red light, while gallium nitride is used for blue-green light. High quality gallium nitride quantum wells require very high growth temperatures (> 1000 ℃) but the early high temperature layers can be destroyed when subsequently growing temperature sensitive phosphide materials. The stacking sequence must be carefully designed, and usually red light, green light and blue light, which are most sensitive to high temperatures, are first made, and finally high temperature-resistant blue light is made, but this still compromises the performance of each color light. Industry is urgent to realize the growth of three-color different quantum wells on one MicroLED chip, and the arrangement of more orderly and compact and higher pixel density, so that the three-color light combination chip design can be performed on one chip. Disclosure of Invention The invention aims to overcome the defects of the prior art, and aims to provide a preparation method of a MicroLED display device based on epitaxial reconstruction, and another aim of the invention is to provide a MicroLED display device based on epitaxial reconstruction. In order to solve the technical problems, the invention provides a preparation method of MicroLED display devices based on epitaxial reconstruction, which comprises the following steps: Forming a first part comprising the steps of: step 11, providing a silicon substrate, and sequentially epitaxially growing a nucleation layer and a buffer layer on the upper surface of the silicon substrate; Step 12, forming a first light emitting structure, including: step 121, epitaxially growing a first N-GaN layer on the upper surface of the buffer layer; step 122, growing a first SiN insulating layer on the first N-GaN layer by chemical vapor deposition; step 123, etching a part of the first SiN insulating layer to the upper surface of the first N-GaN layer to form a first groove; Step 124, epitaxially growing a first selective light source layer, wherein the first selective light source layer fills the first groove; step 125, flattening the upper surfaces of the first SiN insulating layer and the first selective light source layer, and epitaxially growing a first P-GaN layer; Step 13, epitaxially growing a first high-resistance AlGaN layer on the first P-GaN layer; Step 14, forming a second light emitting structure, including: step 141, epitaxially growing a second N-GaN layer on the upper surface of the first high-resistance AlGaN layer; step 142, growing a second SiN insulating layer on the second N-GaN layer by chemical vapor deposition; Step 143, etching a part of the second SiN insulating layer to the upper surface of the second N-GaN layer to form a second groove; Step 144, epitaxially growing a second selective light source layer, wherein the second selective light source layer fills the second groove; step 145, flattening the upper surfaces of the second SiN insulating layer and the second selective light source layer, and epitaxially growing a second P-GaN layer; step 15, epitaxially growing a second high-resistance AlGaN layer on the second P-GaN layer; step