CN-121985651-A - Optoelectronic solid state array

Abstract

The present application relates to optoelectronic solid state arrays. The application discloses a structure and a method for manufacturing an optoelectronic solid state array device. In one case, the back plate and the array of micro devices are aligned and connected by bumps.

Inventors

• Goramariza Chaji
• GAO MEI
• Essanola Fatty
• Pranav gavernini

Assignees

• 维耶尔公司

Dates

Publication Date

20260505

Application Date

20200221

Priority Date

20190221

Claims (10)

1. 1. A method of fabricating an array of micro devices, the method comprising: providing a substrate having one or more micro devices, the top surfaces of the micro devices having bumps; providing a back plate comprising one or more bumps corresponding to bumps on the micro device; planarizing the space between the micro device and the bump using at least one planarizing layer; Patterning the at least one planarization layer to clear the bump; The micro device is aligned and brought into contact with the backplate and the at least one planarizing layer is cured.
2. 2. The microdisplay of claim 1, the method further comprising applying pressure prior to curing the at least one planarizing layer.
3. 3. The microdisplay of claim 1, wherein the at least one planarizing layer is an adhesive layer.
4. 4. The micro display of claim 1, the method further comprising: A passivation layer is provided on or over the micro device prior to the adhesive layer.
5. 5. The microdisplay of claim 1, wherein the passivation layer is a dielectric layer, a black matrix, or a reflective layer.
6. 6. The micro display of claim 1, wherein patterning the at least one planarizing layer comprises removing excess adhesive from a top surface of the bump.
7. 7. The microdisplay of claim 1, wherein patterning the at least one planarizing layer includes removing excess adhesive from one of around the bump, a microdevice, or the top surface of the bump.
8. 8. The micro display of claim 1, wherein patterning the at least one planarization layer comprises patterning the at least one planarization layer by direct photolithography.
9. 9. The micro-display of claim 1, wherein patterning the at least one planarization layer comprises patterning the at least one planarization layer through Shi Fuguang a photoresist layer.
10. 10. The micro-display of claim 1, wherein a surface of the patterned planarization layer is functionalized to bond to some adhesive material.

Description

Optoelectronic solid state array The application is a divisional application of application No. 202080030140.7, entitled "photoelectric solid state array" with application No. 2020, 4 and 23. Cross-reference to related applications The present application claims priority and benefit from U.S. provisional patent application Ser. No. 62/962,027, U.S. provisional patent application Ser. No. 62/947,950, U.S. provisional patent application Ser. No. 62/913,790, and U.S. provisional patent application Ser. No. 62/808,589, and U.S. provisional patent application Ser. No. 21, 2, 2019. Each of these applications is incorporated by reference herein in its entirety. Technical Field The present disclosure relates to optoelectronic solid state array devices and more particularly to bonding micro device arrays to a back plate using reliable methods. Background One of the challenges is implementing selective transfer of micro devices and bonding the micro devices into a backplate. Disclosure of Invention The present disclosure relates to a method of manufacturing an array of micro devices. The method includes providing a substrate having one or more micro devices with bumps on a top surface of the micro devices, providing a back plate including one or more bumps corresponding to the bumps on the micro devices, planarizing a space between the micro devices and the bumps with at least one planarizing layer, patterning the at least one planarizing layer to clear the bumps, aligning and contacting the micro devices with the back plate, and curing the at least one planarizing layer. According to another embodiment, a micro display includes a substrate having one or more micro devices with bumps on a top surface thereof, a back plate including one or more bumps corresponding to the bumps on the one or more micro devices, at least one patterned planarization layer covering a space between the micro devices and the bumps, wherein the substrate and the back plate are aligned and connected by curing the at least one patterned planarization layer. According to yet another embodiment, a method of manufacturing an array of micro devices may include the steps of providing an array of micro devices having bumps on a top surface of a substrate, forming at least one common contact at one or more common layers of the substrate, forming a bridge for the common contact to approximate a height of the micro devices, forming an electrode to bring the common contact to a top of the bridge, forming at least one common bump on top of the electrode, providing a back plate including one or more bumps corresponding to the common bump and the bump on the micro devices, aligning and contacting the micro devices with the back plate, and bonding the micro devices and the back plate together by bumps. Drawings The foregoing and other advantages of the disclosure will become apparent upon reading the following detailed description and upon reference to the drawings. FIG. 1A shows a flow chart illustrating a method according to one embodiment of the invention. FIG. 1B shows another flow chart illustrating a method according to one embodiment of the invention. Figure 2A shows a cross-sectional view of an array of micro devices on a micro device substrate according to one embodiment of the invention. Fig. 2B shows a cross-sectional view of the micro device array of fig. 2A after patterning an adhesive layer, according to one embodiment of the invention. Figure 2C shows a cross-sectional view of an array of micro devices aligned with a back plate, according to one embodiment of the invention. Figure 2D shows a cross-sectional view of an array of micro devices bonded to a back plate by bumps according to one embodiment of the invention. Figure 2E shows a cross-sectional view of an array of micro devices bonded to a backplate and a planarization layer according to one embodiment of the invention. Figure 3A shows a cross-sectional view of an array of micro devices according to one embodiment of the invention. Figure 3B shows a cross-sectional view of an array of micro devices with bumps according to one embodiment of the invention. Fig. 4A shows a cross-sectional view of a micro device array according to an embodiment of the invention. Fig. 4B shows a top view of an array of micro devices according to one embodiment of the invention. Figures 4C through 4E show cross-sectional views of an array of micro devices according to an embodiment of the invention. Figure 5A shows a cross-sectional view of a micro device array having bumps, a dielectric layer, and a planarizing layer in accordance with an embodiment of the present invention. Figure 5B shows a cross-sectional view of a micro device array with bumps and etched dielectric and planarizing layers in accordance with an embodiment of the invention. Fig. 6A shows the formation of bond pads on a substrate and the patterning of an adhesive layer to form nanopillars. Fig. 6B shows that the adhesive in the post is expos