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CN-121985666-A - Power diode based on n-Si/(n-Si) - (ZIF-8)/Ag composite structure, 3D packaging chip and application

CN121985666ACN 121985666 ACN121985666 ACN 121985666ACN-121985666-A

Abstract

The invention discloses a power diode based on MOF, a preparation method, a 3D chip packaging method and application thereof, belongs to the technical field of electronic materials and power devices, and particularly relates to an n-Si substrate/"(n-Si) - (ZIF-8) composite layer"/Ag layer composite structure, a preparation method, a 3D chip packaging method and application thereof in the field of power devices. The reverse withstand voltage of the power diode based on the n-Si substrate/"(n-Si) - (ZIF-8) composite layer"/Ag layer composite structure exceeds 200V, the forward conducting voltage of the power diode is 0.25-1.5V, the reverse bias voltage of the power diode is 0-200V, the reverse leakage current is not basically increased along with the increase of the reverse bias voltage, and the reverse leakage current is 0.2-2.1 mA (at the reverse voltage of-100V). Compared with a conventional power diode based on an n-Si substrate/Ag layer Schottky structure, the forward voltage is increased by 80-400% although the forward voltage is basically unchanged, the reverse saturation current is reduced by 50-800%, and the yield is up to 95%.

Inventors

  • ZENG WEI
  • GUO ZHIDONG
  • CHEN YIMING
  • CAI YAO
  • XIONG DAI
  • Wang Faniu

Assignees

  • 安徽大学

Dates

Publication Date
20260505
Application Date
20260205

Claims (10)

  1. 1. An n-Si/(n-Si) - (ZIF-8)/Ag composite structure sequentially comprises an n-Si substrate layer, an (n-Si) - (ZIF-8) composite layer and an Ag layer from bottom to top.
  2. 2. The composite structure of claim 1, wherein in the (N-Si) - (ZIF-8) composite layer internal structure, zn atoms in the ZIF-8, si atoms in the N-Si and-OH on the N-Si surface form Si-O-Zn bonds together, wherein between the N-Si substrate layer and the (N-Si) - (ZIF-8) composite layer, P atoms in the N-Si substrate layer, P atoms on the N-Si substrate layer, OH on the N-Si surface inside the (N-Si) - (ZIF-8) composite layer, and Zn atoms on the ZIF-8 inside the (N-Si) - (ZIF-8) composite layer form P-O-Zn bonds together, wherein between the Ag atoms in the Ag layer and the (N-Si) - (ZIF-8) composite layer, ag-N bonds are formed together, wherein the Ag layer forms a thin film structure with the (N-Si) - (ZIF-8) composite layer, and wherein the Schottky junction force is formed between the Ag layer and the Si substrate layer by the Schottky junction force.
  3. 3. The composite structure of claim 1, wherein the n-Si substrate layer has a thickness of 0.01 to 2.0 mm, preferably 0.1 to 1.0 mm, more preferably 0.3 to 0.6 mm, the (n-Si) - (ZIF-8) composite layer has a thickness of 0.1 to 1000 nm, preferably 1 to 500 nm, more preferably 10 to 200 nm, and the ag layer has a thickness of 1 to 1000 nm, preferably 10 to 500 nm, more preferably 30 to 200 nm.
  4. 4. The preparation method of the composite structure according to any one of claims 1-3, firstly etching an n-Si substrate, then performing electrodeposition on the etched n-Si substrate by adopting ZIF-8 electroplating solution to obtain an (n-Si) - (ZIF-8) composite layer, and then performing deposition of an Ag layer, wherein the ZIF-8 electroplating solution is prepared by dissolving sodium hyaluronate powder in deionized water, then adding ethanol, mixing uniformly, and then adding ZIF-8 powder into the mixed solution, and the deposition of the Ag layer is performed by adopting a vacuum evaporation thermal evaporation method.
  5. 5. A schottky type power diode based on the composite structure of any one of claims 1-3 or based on the composite structure obtained by the manufacturing method of claim 4.
  6. 6. The schottky power diode of claim 5 wherein the composite structure is used as a substrate and the Ag layer/n-Si substrate/(n-Si) - (ZIF-8) composite layer/Ag layer is obtained by depositing an Ag layer on the back of the n-Si substrate layer.
  7. 7. A composite power diode chip is obtained by taking the Schottky power diode as a basic unit, and adopting a 3D heterogeneous packaging structure to carry out packaging connection on at least three Schottky power diodes.
  8. 8. The composite power diode chip as recited in claim 7, wherein the three Schottky power diodes are packaged in a 3D heterogeneous package structure, and the three Schottky power diodes mainly comprise a bottom heat dissipation interconnection structure, a middle functional layer and an outer package protection structure, The bottom heat dissipation interconnection structure comprises an aluminum oxide ceramic heat dissipation substrate and an insulating substrate, wherein a rectangular embedded clamping groove is etched in the insulating substrate; The middle functional layer comprises a left area and a right area, wherein the left area is provided with two Schottky power diodes, and the right area is provided with one Schottky power diode; the upper layer is a horizontal front-mounted Schottky power diode unit SC2, the surface of the upper layer is covered with a second PI medium isolation layer, the cathode of the SC2 is connected to the cathode of the SC1 through the conductive silver paste and connected with a bottom microstrip network through the vertical interconnection cavity, and the surface of the first PI medium layer is connected with a bottom microstrip network in a bridging way; the right area is a vertical embedded schottky power diode unit SC3 which is precisely embedded in a rectangular clamping groove of the insulating substrate, and an anode and a cathode of the SC3 are respectively connected to a bottom microstrip line network through conductive silver paste; the outer layer packaging protection structure is formed by packaging epoxy resin to form a coating layer, and polishing after curing to expose the lateral wide and high surfaces of the alumina ceramic substrate to form a transverse heat dissipation path; The bottom layer heat dissipation interconnection structure further comprises five lead frames, the five lead frames penetrate out of the top of the coating layer, wherein each lead frame is connected with the anode of the SC1 through a microstrip line, the second lead frame is connected with the anode of the SC2 through a microstrip line, the third lead frame serves as a common cathode and is connected with a common connection node of the SC1 and the SC2 through a microstrip line, the fourth lead frame is connected with the cathode of the SC3 through a microstrip line, and the fifth lead frame is connected with the anode of the SC3 through a microstrip line.
  9. 9. The method of packaging a schottky composite power diode chip of claim 8, comprising: Firstly, carrying out plasma cleaning on an alumina ceramic plate, fixedly connecting an insulating substrate on the surface of the alumina ceramic plate, forming a jogged clamping groove in the insulating substrate through deep reactive ion etching, filling the clamping groove with soluble polyvinyl alcohol PVA serving as a sacrificial material after the jogged clamping groove is formed in the insulating substrate through etching, and enabling the surface of the alumina ceramic plate to be level with the insulating substrate through chemical mechanical polishing, so that a temporary flat working surface is formed; the method comprises the steps of spin coating a polyimide PI insulating adhesive layer, precisely etching a needed rectangular contact window on the PI layer through a photoetching process and reactive ion etching RIE after the PI layer is coated, finally, dissolving and removing a PVA sacrificial layer through a warm water bath, synchronously realizing the forming of the window on the PI adhesive layer and the emptying of a clamping groove in an insulating substrate, then adopting a vacuum thermal evaporation process and mask patterning to construct a copper wire network of a microstrip line structure on the surface of the PI layer, and realizing the bonding interconnection of the copper wire and five lead frames through gold wire ball welding, wherein the specific connecting frame is that the lead frame is connected to an SC1 anode port through a microstrip line, the lead frame II is connected to an SC2 anode port through the microstrip line, the lead frame III serves as a public cathode, is connected to a joint node of the SC1 and the SC2 through the microstrip line, the lead frame IV is connected to an SC3 cathode port through the microstrip line, and the lead frame V is connected to an SC3 anode port through the microstrip line; The method comprises the steps of carrying out left-region double-layer stacking assembly, carrying out spin coating on the cathode surfaces of an SC1 and an SC2 respectively, windowing by a photoetching process to form a cavity structure for vertical interconnection, filling high-conductivity silver paste in the cavity, leading the silver paste to the edge of the PI layer through a vacuum thermal evaporation process to construct a preliminary interconnection end, carrying out pretreatment, butting the SC1 and the SC2 on the cathode surfaces of the SC1 and the SC2, carrying out solid connection through the PI layer and the silver paste structure to form a preliminary SC1-SC2 stacked body, carrying out integral rotation of the stacked body by 90 degrees to enable the side vertical surface of the stacked body to be upwards used as a new technological plane, sequentially spin coating and curing the PI medium layer, constructing a copper wire of a microstrip line structure on the side surface by adopting a magnetron sputtering process, carrying out a single-piece unit on the stacked body with the completed side surface vertically interconnected, leading the SC1 anode to be downwards, using the conductive silver paste to be bonded to a copper wire node of a bottom layer, finally spin coating on the upper surface of the SC2 through the PI layer, carrying out solid connection through the PI layer and realizing solid connection through the PI layer structure, carrying out spin coating on the SC1-SC2, carrying out lateral surface opening and forming a microstrip line structure, carrying out lateral heat radiation on the surface of the stacked body, carrying out a lateral connection on the surface of the stacked body, carrying out a microstrip line structure, and carrying out a lateral connection, and carrying out a lateral heat radiation on the copper wire structure, and carrying out a lateral connection on the surface of the copper wire structure, and carrying out a microstrip line structure, and forming a lateral connection structure, and carrying out a lateral connection structure.
  10. 10. The schottky composite power diode chip according to claim 7 or 8 or the use of the schottky composite power diode chip obtained by the method according to claim 9, characterized in that the schottky composite power diode chip comprises at least one functional unit of a single-channel schottky rectifying unit, a bipolar overvoltage protection unit, a high-voltage cascade withstand voltage unit, a two-phase common-cathode rectifying topology unit and a cascade current-resistant extension unit, wherein, The single-channel Schottky rectifying unit can be applied to at least one of a rectifying unit in a high-frequency switching power supply, a polarity protection circuit of a photovoltaic inverter and reverse voltage protection of low-power-consumption equipment; the bipolar overvoltage protection unit can be applied to at least one of voltage clamping protection in an alternating current circuit, an ESD protection module of communication equipment and transient voltage suppression of a vehicle-mounted electronic system; the high-voltage cascade voltage-resistant unit can be applied to at least one of a high-voltage direct-current power input stage, a pre-charging loop of an electric automobile charging pile and busbar voltage division protection of an industrial frequency converter; the two-phase common cathode rectification topological unit can be applied to at least one of common cathode topology of a two-phase alternating current rectification bridge, common ground isolation of a multichannel data acquisition system and an anti-crosstalk protection circuit of a high-precision ADC input stage; the cascade current-resistant expansion unit can be applied to at least one of a high-power AC/DC converter pre-voltage stabilizing stage, an PFC rectifying stage of an OBC of an electric automobile and an industrial high-current load redundancy protection circuit.

Description

Power diode based on n-Si/(n-Si) - (ZIF-8)/Ag composite structure, 3D packaging chip and application Technical Field The invention belongs to the technical field of electronic materials and power devices, and particularly relates to an n-Si substrate/"(n-Si) - (ZIF-8) composite layer"/Ag layer composite structure, a preparation method, a 3D chip packaging method and application thereof in the field of power devices. Background Along with the rapid development of technology, the microelectronic technology is taken as the basic strength of the electronic information technology, is the core technology of the information industry, and the material is taken as the material foundation and supporting industry of social development and modern economy, thus being an important research direction of microelectronics and playing a very important role in the development of society. In combination with the background of the current age, the electric automobile, renewable energy sources and digital revolution are rising, and the global power diode market continues to benefit from the rapid growth in the fields of electric automobiles, renewable energy sources, digital transformation and the like. The power semiconductor is used as a core for electric energy conversion and circuit control of the power electronic device, can realize the functions of frequency conversion, phase conversion, voltage transformation, inversion and the like, has irreplaceable key roles in the current application fields of high power, high current, high frequency, high speed and the like, and particularly has the aspects of pressure resistance, conductivity, thermal management, energy efficiency and the like. The traditional semiconductor materials such as germanium (Ge), crystalline silicon (Si), gallium nitride (GaN) and the like have complex preparation process and extremely high requirements on precision and quality of equipment, greatly increase process energy consumption and production cost, and cannot well meet the requirements of modern high-efficiency use. Therefore, the research is based on new principles, new materials, new structures and more excellent performances, and the preparation of cheaper types becomes an urgent need in the current scientific research and production fields. MOF (metal organic framework) is an extremely versatile super porous nanomaterial that can be used to store, separate, release, modify almost anything. Scientists have designed more than 88000 precisely tailored MOFs, ranging from agriculture to industry. The unique structure and chemical properties of the MOF material enable the MOF material to have good insulation property and voltage resistance under an electric field. By optimizing the crystal structure and the components of the MOF, the voltage resistance of the MOF can be improved, and the safety and the reliability of the power device are further improved. In the device design, the interface defect can be reduced and the voltage withstanding characteristic can be enhanced by precisely regulating and controlling the interface between the MOF and other materials. The interface optimization can effectively reduce current leakage and improve the withstand voltage level of the device. In paper "Graphene-silicon Schottky devices for operation in aqueous environments: Device performance and sensing application"(ACS Applied Materials & Interfaces.14.38.43131-43140) , a preparation method of a Schottky junction is introduced, single-layer graphene grown by adopting an n-type Si substrate through a wet transfer technology and integrating CVD is adopted, a Cr/Au composite electrode (5-50 nm) is deposited by adopting electron beam evaporation, and annealing at 350-450 ℃ is carried out in a nitrogen environment to optimize interface contact, so that typical Schottky characteristics are represented. And testing the volt-ampere characteristic curve of the Schottky junction to obtain an IV curve graph, and drawing the IV characteristic curve of the Schottky junction to obtain the rectification ratio of 6.2 multiplied by 10 2 at 0.3V, wherein the value of the rectification ratio is smaller. In paper "Graphene-Silicon Schottky Diodes" (Nano letters.11.5.1863-1867), a preparation method of a Schottky junction is described, vertical oriented Graphene nanowalls are directly grown on heavily doped n+ Si, ti/Pt/Au (20/30/100 nm) interdigital electrodes are prepared by magnetron sputtering, interface defects are eliminated by rapid thermal annealing, and typical Schottky characteristics are shown. According to the voltammetric characteristic curve of the Schottky junction tested in the literature, the rectification ratio at 0.3V is 0.8X10 3, and the value of the rectification ratio is small. Disclosure of Invention Aiming at the problems in the prior art, the invention provides an n-Si substrate/"(n-Si) - (ZIF-8) composite layer"/Ag layer composite structure, a preparation method, a 3D chip packaging method and application,