CN-121985724-A - Method for manufacturing semiconductor structure

Abstract

The application provides a manufacturing method of a semiconductor structure, which is applied to the technical field of semiconductors. In the application, the piezoelectric effect of the piezoelectric material layer is utilized by combining the mode of forming the piezoelectric material layer between the substrate and the high-k dielectric layer, the embedded epitaxial process, the stress memory technology and other processes, and the mechanical stress generated by the embedded epitaxial process, the stress memory technology and other processes is converted into a vertical electric field, so that the mobility of electrons or holes of the transistor is improved.

Inventors

• JIANG LINFENG
• Li Qiumao
• LIN ZHAOHONG

Assignees

• 重庆芯联微电子有限公司

Dates

Publication Date

20260505

Application Date

20251229

Claims (10)

1. 1. A method of fabricating a semiconductor structure, comprising: providing a substrate, wherein the substrate comprises a PMOS region; forming a piezoelectric material layer on the substrate of the PMOS region; Forming a high-k dielectric layer on the piezoelectric material layer; And forming a source-drain groove in the PMOS region, and filling an embedded epitaxial layer in the source-drain groove.
2. 2. The method of fabricating a semiconductor structure of claim 1, wherein the material of the piezoelectric material layer comprises molybdenum disulfide.
3. 3. The method of claim 1, wherein the thickness of the piezoelectric material layer in the vertical direction is in a range of 3 angstrom to 5 angstrom.
4. 4. The method of fabricating a semiconductor structure according to claim 1 or 2, further comprising, prior to forming the layer of piezoelectric material: An adhesion layer is formed on the substrate for preventing peeling of the piezoelectric material layer.
5. 5. The method of fabricating a semiconductor structure of claim 4, wherein the material of the adhesion layer comprises aluminum oxide.
6. 6. The method of claim 4, wherein the thickness of the adhesion layer in the vertical direction is in the range of 3 a to 5 a.
7. 7. The method of claim 1, wherein the substrate further comprises an NMOS region, and the layer of piezoelectric material further extends onto the substrate of the NMOS region.
8. 8. The method of manufacturing a semiconductor structure according to claim 7, further comprising, after filling the source-drain trench with the embedded epitaxial layer: Forming a tensile stress memory layer on the substrate; performing a high temperature anneal on the substrate; and removing the tensile stress memory layer.
9. 9. The method of fabricating a semiconductor structure according to claim 8, further comprising, after removing the tensile stress memory layer: And forming a contact hole etching stop layer on the substrate of the PMOS region and the NMOS region.
10. 10. The method of fabricating a semiconductor structure of claim 1, further comprising, prior to forming the layer of piezoelectric material: An oxide layer is formed on the substrate.

Description

Method for manufacturing semiconductor structure Technical Field The application relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure. Background With the continuous improvement of chip performance requirements, in the existing High-dielectric-constant metal gate (High-K METAL GATE, HKMG) process, hole/electron mobility is mainly increased by means of a silicon germanium (SiGe) process, a stress memory technology (Strained Silicon Technology, SMT), a contact hole etching stop layer (Contact Etch Stop Layer, CESL) technology and the like, but it is very difficult to further improve carrier mobility on the basis of the hole/electron mobility, and it is difficult to meet the High-performance chip requirements. Meanwhile, in order to improve the interface quality between the high-k material, such as hafnium oxide (HfO 2), and the substrate, and reduce interface defects and carrier scattering, so as to improve the performance of the transistor, a very thin oxide layer, such as silicon dioxide (SiO 2), is usually formed under the high-k dielectric layer, and a certain interface state density exists between HfO 2 and SiO 2 on the substrate, so that carrier scattering and threshold voltage drift are easily caused. Disclosure of Invention The application aims to provide a manufacturing method of a semiconductor structure, which utilizes the piezoelectric effect of a piezoelectric material layer in a mode of combining a piezoelectric material layer formed between a substrate and a high-k dielectric layer with processes such as an embedded epitaxial process and a stress memory technology to convert mechanical stress generated by the processes such as the embedded epitaxial process and the stress memory technology into a vertical electric field, thereby improving the mobility of electrons or holes of a transistor. In order to solve the above technical problems, the present application provides a method for manufacturing a semiconductor structure, which at least includes the following steps: providing a substrate, wherein the substrate comprises a PMOS region; forming a piezoelectric material layer on the substrate of the PMOS region; Forming a high-k dielectric layer on the piezoelectric material layer; And forming a source-drain groove in the PMOS region, and filling an embedded epitaxial layer in the source-drain groove. Further, the material of the piezoelectric material layer comprises molybdenum disulfide. Further, the thickness range of the piezoelectric material layer in the vertical direction is 3-5 angstroms. Further, before forming the piezoelectric material layer, the method further includes: An adhesion layer is formed on the substrate for preventing peeling of the piezoelectric material layer. Further, the material of the adhesion layer includes alumina. Further, the thickness of the adhesion layer in the vertical direction ranges from 3 angstroms to 5 angstroms. Further, the substrate further comprises an NMOS region, and the piezoelectric material layer further extends onto the substrate of the NMOS region. Further, after filling the embedded epitaxial layer in the source-drain trench, the method further comprises: Forming a tensile stress memory layer on the substrate; performing a high temperature anneal on the substrate; and removing the tensile stress memory layer. Further, after removing the tensile stress memory layer, the method further includes: And forming a contact hole etching stop layer on the substrate of the PMOS region and the NMOS region. Further, before forming the piezoelectric material layer, the method further includes: An oxide layer is formed on the substrate. Compared with the prior art, the technical scheme of the application has at least one of the following beneficial effects: In the manufacturing method of the semiconductor structure, the piezoelectric material layer is formed between the substrate of the PMOS region and the high-k dielectric layer, the source-drain groove is formed in the PMOS region, and the embedded epitaxial layer is filled in the source-drain groove, so that the piezoelectric effect of the piezoelectric material layer is utilized to convert mechanical stress into a vertical electric field, and the hole mobility of the PMOS tube is improved. Further, an adhesive layer is formed on the substrate for preventing peeling of the piezoelectric material layer. Further, the piezoelectric material layer extends to the substrate of the NMOS region, after the embedded epitaxial layer is filled in the source drain groove, a tensile stress memory layer is formed on the substrate, high-temperature annealing is performed on the substrate, and finally the tensile stress memory layer is removed, so that the piezoelectric effect of the piezoelectric material layer is utilized to convert mechanical stress into a vertical electric field, and the electron mobility of the NMOS tube is improved. Further, after the