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CN-121985731-A - Method for manufacturing interconnection salient points and application thereof

CN121985731ACN 121985731 ACN121985731 ACN 121985731ACN-121985731-A

Abstract

The application discloses a method for manufacturing an interconnection bump and application thereof, belonging to the field of quantum computation. The method of manufacturing an interconnect bump includes obtaining a base of a lift-off layer and a bump layer covered by a patterned mask, grinding a substrate such that the lift-off layer is removed to expose the mask, and stripping the mask to form a bump layer independently present on the substrate. The interconnection bump formed in the above manner has higher quality.

Inventors

  • JIA ZHILONG
  • Request for anonymity
  • Request for anonymity
  • Request for anonymity

Assignees

  • 本源量子计算科技（合肥）股份有限公司

Dates

Publication Date
20260505
Application Date
20241028

Claims (10)

  1. 1. A method of manufacturing an interconnect bump, comprising: Obtaining a substrate, wherein the substrate is provided with a substrate, a patterned mask on the surface of the substrate and a plating layer formed on the basis of the patterned mask, and the plating layer comprises a stripping layer on the surface of the mask and a bump layer which is positioned in a hole of the mask and is in contact with the surface of the substrate; Grinding the substrate to remove the peeling layer to expose the mask, and And stripping the mask to form a bump layer independently existing on the substrate.
  2. 2. The method of manufacturing an interconnect bump of claim 1 wherein the substrate surface is provided by a metal layer attached to the substrate; optionally, the metal layer is directly attached to the substrate; optionally, the material of the metal layer is superconducting metal, or the metal layer comprises aluminum or tantalum.
  3. 3. The method of manufacturing an interconnect bump of claim 1 wherein the patterned mask is photoresist exposed and developed; Optionally, the method for stripping the mask comprises the steps of stripping the substrate in stripping liquid to remove the mask; Optionally, the stripping solution is heated N-methylpyrrolidone, or the stripping solution is subjected to an ultrasonic treatment during the stripping treatment.
  4. 4. The method of manufacturing an interconnect bump of claim 1 wherein the material of the plating is indium.
  5. 5. The method of manufacturing an interconnect bump according to claim 1 or 4, characterized in that the peeling layer and the bump layer are manufactured in the same step.
  6. 6. The method of manufacturing an interconnect bump according to claim 1, wherein the method of polishing to remove the peeling layer is chemical mechanical polishing; Optionally, during chemical mechanical polishing, the substrate is secured to the substrate by embedding or bonding the substrate, the substrate having an area smaller than the substrate.
  7. 7. The method of manufacturing an interconnect bump of claim 1 or 6 wherein the endpoint of the lapping is determined based on the reflectivity of the substrate.
  8. 8. The method of manufacturing an interconnect bump of claim 7 wherein the method of determining the endpoint of lapping by the reflectivity of the substrate comprises: the reflectivity of the substrate is continuously detected during the polishing process, and when the value of the reflectivity exceeds a preset fluctuation range, the polishing endpoint is determined at the moment.
  9. 9. A substrate having a conductive bump on a surface formed by carrying out the method of manufacturing an interconnect bump according to any one of claims 1 to 8.
  10. 10. Use of the method for manufacturing an interconnect bump as claimed in any one of claims 1 to 8 for manufacturing a flip-chip superconducting quantum chip.

Description

Method for manufacturing interconnection salient points and application thereof Technical Field The application belongs to the field of quantum information, in particular to the field of quantum computation, and particularly relates to a method for manufacturing an interconnection bump and application thereof. Background Flip-chip bonding is a packaging scheme that enables high density, high efficiency electrical connections. The core of this package approach is the use of bump interconnects instead of traditional bonded wire interconnects. Indium has a melting point of 156 ℃ and a boiling point of 2080 ℃. As a soft metal with a low melting point, the intrinsic stress of indium can be rapidly removed at room temperature. Compared with other interconnection materials, the metal indium has better ductility and shearing strength, so that the thermal stress in the partial flip-chip device can be offset to a certain extent. And indium has excellent flexibility at normal temperature, so that bonding can be easily realized by indium. Meanwhile, indium is superconducting in a temperature environment where the superconducting quantum chip works. Indium is also preferably used to manufacture indium bumps by evaporation. Therefore, indium metal is a desirable interconnect material for flip-chip packaging. For flip-chip packaging technology, the preparation of indium bumps is critical. Disclosure of Invention Examples of the present application provide a method of manufacturing an interconnection bump and application thereof, which can realize high-quality bump manufacturing, thereby contributing to improvement of flip chip quality. The exemplary embodiment of the present application is implemented as follows. In a first aspect, the present application discloses a method of manufacturing an interconnect bump, comprising: Obtaining a substrate, wherein the substrate is provided with a substrate, a patterned mask on the surface of the substrate and a plating layer formed on the basis of the patterned mask, and the plating layer comprises a stripping layer on the surface of the mask and a bump layer which is positioned in a hole of the mask and is contacted with the surface of the substrate; Grinding the substrate to remove the peeling layer to expose the mask, and The mask is stripped to form a bump layer independently existing on the substrate. According to some examples of the application, the substrate surface is provided by a metal layer attached to the substrate; Optionally, the metal layer is directly attached to the substrate; Optionally, the material of the metal layer is superconducting metal, or the metal layer includes aluminum or tantalum. According to some examples of the application, the patterned mask is formed by exposing and developing photoresist; optionally, the method for stripping the mask comprises the steps of stripping the substrate in stripping liquid to remove the mask; Optionally, the stripping solution is heated N-methylpyrrolidone, or the stripping solution is subjected to an ultrasonic treatment during the stripping treatment. According to some examples of the application, the material of the plating layer is indium. According to some examples of the application, the release layer and the bump layer are manufactured in the same step. According to some examples of the application, the method of polishing to remove the release layer is chemical mechanical polishing; optionally, during chemical mechanical polishing, the substrate is secured to the substrate by embedding the substrate or bonding, the substrate having an area smaller than the substrate. According to some examples of the application, an endpoint of the grinding is determined based on a reflectivity of the substrate. According to some examples of the application, a method of determining an endpoint of polishing by reflectivity of a substrate includes: the reflectivity of the substrate is continuously detected during the polishing process, and when the value of the reflectivity exceeds a preset fluctuation range, the polishing endpoint is determined at the moment. In a second aspect, the present application discloses a substrate having conductive bumps on a surface formed by implementing the above method of manufacturing an interconnect bump. In a third aspect, the present application discloses an application of the method for manufacturing an interconnection bump in manufacturing a flip-chip superconducting quantum chip. In the implementation process, the photoresist is subjected to grinding operation before stripping to remove the plating layer on the surface of the photoresist, and then stripping is performed to form the interconnection bump. In this way, the top surface of the photoresist is free of plating material residue during the stripping operation, so that there is no substrate surface with plating material residue during stripping, while also ensuring that the photoresist is adequately stripped. By the method, high-quali