CN-121985734-A - In-situ growth SnS2Preparation method of low-power-consumption high-switching-ratio resistance random access memory

Abstract

The invention relates to a preparation method of an in-situ growth SnS 2 low-power-consumption high-switching-ratio resistance random access memory. The preparation method comprises the steps of sequentially processing a Cr layer and an Au layer on the surface of a wafer-level SiO 2 /Si substrate to obtain a Cr/Au bottom electrode, and completing preparation of a SnS 2 resistance change layer by a PrCVD method to obtain an in-situ grown PMMA/SnS 2 /Au sample, wherein a hard mask technology is adopted to process an Ag metal film, so that preparation of the in-situ grown SnS 2 low-power-consumption high-switching-ratio resistance change memory is completed. The invention can prepare the two-dimensional material growing in the vertical direction, and can effectively reduce the power consumption of the resistive random access memory. The target product can directly finish growth on the surface of the substrate, so the invention can directly deposit a large-area two-dimensional material on the surface of the metal. The preparation process has good stability, and the prepared wafer-level SnS 2 resistive random access memory can be used as a master slice for industrial production, can also enter a CMOS process production flow, and greatly promotes the industrialization of the low-power-consumption high-switching-ratio resistive random access memory based on two-dimensional materials.

Inventors

• Jian Jiaying
• Dong Pifan
• Gao Shukan
• LI JINGJUN
• JIN CHANGQING
• WEI YONGXING
• NAN RUIHUA
• GAO LING

Assignees

• 西安工业大学

Dates

Publication Date

20260505

Application Date

20260205

Claims (8)

1. 1. The preparation method of the in-situ growth SnS 2 low-power consumption high-switching-ratio resistance random access memory is characterized by comprising the following steps: Preparing a bottom electrode, namely sequentially processing Cr/Au metal layers on the surface of a wafer-level SiO 2 /Si substrate to obtain a Cr/Au bottom electrode; step two, preparing a SnS 2 resistance variable layer, which comprises the following steps: 2.1, preparing SnS 2 quantum dot-absolute ethyl alcohol solution; 2.2, preparing SnCl 2 -absolute ethanol solution; 2.3, spin-coating the SnS 2 quantum dot-absolute ethyl alcohol and the SnCl 2 -absolute ethyl alcohol solution on the surface of the bottom electrode in the first step; 2.4, carrying out reaction treatment in a double-temperature-zone tube furnace: 2.5, after the reaction is finished and cooled to room temperature, spin-coating a layer of PMMA film on the upper surface of the bottom electrode to obtain an in-situ grown PMMA/SnS 2 /Au sample; Step three, preparing a top electrode: and covering a hard mask on the surface of the PMMA/SnS 2 /Au sample, processing an Ag metal film, and removing the mask to finish the preparation of the in-situ growth SnS 2 low-power-consumption high-switching-ratio resistance random access memory.
2. 2. The method for preparing the in-situ grown SnS 2 low-power consumption high-switching-ratio resistive random access memory according to claim 1, wherein in the first step, the thickness of the Cr/Au bottom electrode is 3-10/100-1000 nm.
3. 3. The method for preparing the in-situ grown SnS 2 low-power consumption high-switching-ratio resistive random access memory according to claim 1, wherein in the step 2.1, the mass concentration of the SnS 2 quantum dot-absolute ethyl alcohol is 0.001-0.01g/ml.
4. 4. The method for preparing the in-situ grown SnS 2 low-power consumption high-switching-ratio resistive random access memory according to claim 1, wherein in the step 2.2, the mass concentration of the SnCl 2 -absolute ethyl alcohol solution is 0.05-0.12 g/ml.
5. 5. The method for preparing the in-situ grown SnS 2 low-power consumption high-switching-ratio resistive random access memory according to claim 1, wherein in the steps 2.3 and 2.5, the rotating speed of spin coating is 500-8000 rmp.
6. 6. The method for preparing the in-situ grown SnS 2 low-power consumption high-switching-ratio resistive random access memory according to claim 5, wherein the preferred spin-coating rotating speed is 2000-6000rmp.
7. 7. The method for preparing the in-situ growth SnS 2 low-power consumption high-switching-ratio resistance-changing memory is characterized in that the specific steps of the step 2.4 are that a bottom electrode is placed at the downstream of a double-temperature-zone tube furnace, excessive sublimed sulfur is placed at the upstream of the tube furnace, 5%H 2 /Ar mixed gas is continuously introduced after repeated vacuum pumping after the tube furnace is sealed, heating reaction is started after a temperature control program is set, the upstream reaction temperature is set to be 100-300 ℃, the downstream reaction temperature is set to be 300-800 ℃, and the reaction time is 5-120 min.
8. 8. The method for preparing the in-situ grown SnS 2 low-power consumption high-switching-ratio resistive random access memory according to claim 1, wherein in the first step and the third step, the processing mode of the metal film is vacuum thermal evaporation or magnetron sputtering.

Description

Preparation method of in-situ growth SnS 2 low-power-consumption high-switching-ratio resistance random access memory Technical Field The invention belongs to a nonvolatile memory in a CMOS ultra large scale integrated circuit (ULSI), and particularly relates to a preparation method of an in-situ growth SnS 2 low-power consumption high-switching-ratio resistance random access memory. Background The application number is CN20211086108. X, a low-power consumption nano SnS 2 flexible resistive random access memory and a preparation method thereof are disclosed, wherein SnS 2 is prepared by a hydrothermal method, snS 2 suspension is prepared by an ultrasonic stripping method, and a thin film is formed on the surface of a bottom electrode by a vacuum suction filtration method. The ultrasonic stripping method in the preparation process cannot well control the concentration of the suspension, and the vacuum filtration method is highly dependent on manpower, so that the problems of difficult standardization, poor repeatability and the like exist in batch preparation. Meanwhile, because the electrode and the resistive layer are macroscopically and physically combined, the resistive memory has the problem of poor contact of the electrode. In the patent document with the application number of CN202410569593.7, a resistive switching device and a preparation method thereof are disclosed. The chemical vapor transport method is adopted to grow AgCrP-2S-6 crystals, then the AgCrP-2S-6 crystals are mechanically stripped to obtain AgCrP-2S-6 nano sheets, the AgCrP-2S-6 nano sheets are transferred to a device substrate in an auxiliary mode, and then metal electrode deposition is carried out to obtain the resistive random access device. Because the auxiliary transfer technology at the present stage is difficult to finish large-area wafer level operation, and each transfer needs to be positioned according to the crystal shape, the manufacturing efficiency is low, and batch operation is not facilitated. The article named as "new method for pretreatment of CVD diamond coated cemented carbide substrate" refers to a pretreatment chemical vapor deposition method (CVD method) which is widely used for pretreatment of a substrate, for modifying the morphology of the substrate surface so that the substrate surface is smoother or rougher, and also for chemical modification of the substrate surface to improve the adhesion of a target product on the substrate surface. The method mainly comprises the following steps of 1, carrying out ultrasonic treatment on a substrate by using an acidic or alkaline solution, 2, carrying out ultrasonic cleaning on the treated substrate by using an organic solvent such as absolute ethyl alcohol, acetone and the like, and 3, placing the cleaned substrate and reactants in a reaction container for CVD deposition at the same time to obtain a target product. The substrate is usually a Si sheet, a sapphire sheet, a quartz sheet, a mica sheet and the like with extremely flat surfaces and is used for transversely preparing two-dimensional material crystals. However, the method is difficult to directly deposit a large-area two-dimensional material on the metal surface with a certain thickness, and meanwhile, the conditions of high reactant concentration, dense nucleation sites and the like required by the vertical growth of the two-dimensional material cannot be provided, so that when the prepared transverse two-dimensional material is used for a resistive random access memory with a vertical structure, the conductive filaments have to overcome the high driving force caused by a dense resistive random access layer, and the problems of high SET voltage, poor cycle times and the like exist. Disclosure of Invention The invention provides a preparation method of an in-situ growth SnS 2 low-power consumption high-switching-ratio resistive random access memory, which aims to solve the problems that in the prior art, a large-area two-dimensional material is difficult to directly deposit on a metal surface with a certain thickness, and meanwhile, when the prepared transverse two-dimensional material is used for the resistive random access memory with a vertical structure, a conductive filament is required to overcome high driving force caused by a compact resistive random access layer, and the SET voltage is high and the cycle number is poor. In order to achieve the purpose, the technical scheme provided by the invention is that the preparation method of the in-situ growth SnS 2 low-power-consumption high-switching-ratio resistance random access memory comprises the following steps: Preparing a bottom electrode, namely sequentially processing Cr/Au metal layers on the surface of a wafer-level SiO 2/Si substrate to obtain a Cr/Au bottom electrode; step two, preparing a SnS 2 resistance variable layer, which comprises the following steps: 2.1, preparing SnS 2 quantum dot-absolute ethyl alcohol solution; 2.2, preparing SnCl 2