CN-121985744-A - Treatment of reinforcing material structures

Abstract

A method of forming a semiconductor structure includes the steps of pre-cleaning a surface of a substrate, forming an interface layer on the pre-cleaned surface of the substrate, depositing a high-k dielectric layer on the interface layer, performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer, and performing a post-nitridation annealing process to passivate chemical bonds in the plasma nitrided high-k dielectric layer.

Inventors

• Steven C.H. Hong
• Johannes Swinberg
• MALCOLM BEVAN

Assignees

• 应用材料公司

Dates

Publication Date

20260505

Application Date

20211108

Priority Date

20201106

Claims (6)

1. 1. A method of forming a semiconductor structure, the method comprising: Pre-cleaning the surface of the substrate; Depositing a high-k dielectric layer on the substrate; performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer, and A post nitridation anneal and reoxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-k dielectric layer and thermally oxidize the substrate.
2. 2. The method of claim 1, further comprising the step of An interface layer is formed on the pre-cleaned surface of the substrate to thermally oxidize the substrate with nitrous oxide (N 2 O) gas, wherein the interface layer comprises silicon oxide (SiO 2 ).
3. 3. The method of claim 1, wherein the high-k dielectric layer comprises hafnium oxide (HfO 2 ).
4. 4. The method of claim 1, wherein the plasma nitridation process comprises exposing the deposited high-k dielectric layer to a nitrogen plasma using a mixture of nitrogen (N 2 ) and ammonia (NH 3 ).
5. 5. A processing system, comprising: A first processing chamber; a second processing chamber; a third processing chamber; A fourth processing chamber, and The controller of the system is provided with a controller, the system controller is configured to: Pre-cleaning a surface of a substrate in the first processing chamber; Depositing a high-k dielectric layer on the substrate in the second processing chamber; in the third processing chamber, performing a plasma nitridation process to expose the deposited high-k dielectric layer to a nitrogen plasma, and In the fourth processing chamber, a post-nitridation anneal and reoxidation process is performed to simultaneously passivate the remaining chemical bonds in the high-k dielectric layer and thermally oxidize the substrate, Wherein the substrate is transferred between the first, second, third and fourth processing chambers without breaking a vacuum environment in the processing system.
6. 6. The processing system of claim 5, further comprising: a fifth processing chamber, wherein the system controller is further configured to; An interface layer is formed on the pre-cleaned surface of the substrate to thermally oxidize the substrate with nitrous oxide (N 2 O) gas, wherein the interface layer comprises silicon oxide (SiO 2 ).

Description

Treatment of reinforcing material structures The present application is a divisional application of the application patent application with the application date of 2021, 11/8, the application number of 202111315614.5 and the name of "treatment of reinforcement structure". Technical Field The various embodiments described herein relate generally to semiconductor device fabrication and, more particularly, to systems and methods for forming high quality high-k dielectric material layers in semiconductor structures. Background As Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) have been reduced in size for high device performance and low power consumption, the thickness of conventional silicon dioxide (SiO 2) gate dielectrics has been reduced to its physical limit (PHYSICAL LIMIT). Therefore, to achieve further scaling, it has been unavoidable to replace the silicon dioxide gate dielectric with a high-k dielectric material. Of the various high-k dielectric materials, hafnium oxide (HfO 2) has been applied since the 45nm MOSFET technology node, because of its high dielectric constant and superior thermal stability on silicon substrates. However, for further scaling down of the equivalent oxide thickness (equivalent oxide thickness, EOT) of 32nm MOSFET technology nodes and beyond, simply reducing the thickness of Gao dielectric material layer is problematic because the leakage current through the high-k dielectric material layer increases. Thus, there is a need for systems and methods that can be used to form thin (e.g., EOT less than 1 nm) high- κ dielectric material layers having chemical structures that can be controlled to ensure desired structural and electrical properties. Disclosure of Invention Various embodiments of the present disclosure provide a method of forming a semiconductor structure. The method includes the steps of pre-cleaning a surface of a substrate, forming an interface layer (INTERFACIAL LAYER) on the pre-cleaned surface of the substrate, depositing a high-k dielectric layer on the interface layer, performing a plasma nitridation (plasma nitridation) process to insert nitrogen atoms into the deposited high-k dielectric layer, and performing a post nitridation anneal (post-nitridation anneal) process to passivate chemical bonds in the plasma nitrided high-k dielectric layer. Various embodiments of the present disclosure also provide a method of forming a semiconductor structure. The method includes the steps of pre-cleaning a surface of a substrate, depositing a high-k dielectric layer on the substrate, and performing a plasma nitridation process to insert nitrogen atoms into the deposited high-k dielectric layer. Embodiments of the present disclosure further provide a processing system. The processing system includes a first processing chamber, a second processing chamber, a third processing chamber, a fourth processing chamber, a fifth processing chamber, and a system controller. The system controller is configured to pre-clean a surface of a substrate in the first process chamber, form an interface layer on the pre-cleaned surface of the substrate in the second process chamber, deposit a high-k dielectric layer on the interface layer in the third process chamber, expose the deposited high-k dielectric layer to a nitrogen plasma in the fourth process chamber, and anneal the plasma nitrided high-k dielectric layer in the fifth process chamber. The substrate is transferred between the first, second, third, fourth, and fifth processing chambers without breaking a vacuum environment in the processing system. Drawings So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments. FIG. 1 is a schematic top view of an example multi-chamber processing system according to one embodiment. Fig. 2 is a process flow diagram of a method of forming a semiconductor structure, according to one embodiment. Fig. 3A and 3B are schematic diagrams of a semiconductor structure according to an embodiment. To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation. Detailed Description As gate structures shrink to smaller dimensions, new material structures are continually being sought to provide improvements. The use of high-k dielectric materials increases the dielectric constant of the gate structure compared to