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CN-121985751-A - Method for manufacturing semiconductor structure

CN121985751ACN 121985751 ACN121985751 ACN 121985751ACN-121985751-A

Abstract

The invention provides a method for manufacturing a semiconductor structure. The manufacturing method of the semiconductor structure comprises the steps of providing a groove on the top surface of an intermediate structure, generating an isolation material layer on the intermediate structure, covering the top surface of the intermediate structure and filling the groove, enabling the isolation material layer to comprise a first part and a second part, wherein the first part is located right above the groove, the second part is located on the side edge of the groove, annealing is conducted on the first part, the second part is not annealed, the grinding rate of the first part is smaller than that of the second part, and chemical mechanical grinding is conducted on the isolation material layer and is stopped on a patterned first hard mask layer on the intermediate structure. Thus, the problem of dishing in chemical mechanical polishing can be improved, the process window of chemical mechanical polishing is enlarged, and particularly, the problem that a pattern sparse region is easy to have deeper dishing in chemical mechanical polishing can be improved.

Inventors

  • YANG BIN

Assignees

  • 芯恩（青岛）集成电路有限公司

Dates

Publication Date
20260505
Application Date
20260202

Claims (10)

  1. 1. A method of fabricating a semiconductor structure, comprising: Providing an intermediate structure, wherein the top surface of the intermediate structure is provided with a groove, and the intermediate structure is provided with a patterned first hard mask layer, and the patterned first hard mask layer covers the intermediate structure on the side edge of the groove and exposes the groove; generating an isolation material layer on the intermediate structure, wherein the isolation material layer covers the top surface of the intermediate structure and fills the groove, and the isolation material layer comprises a first part right above the groove and a second part at the side edge of the groove; Annealing the first portion without annealing the second portion such that the first portion has a lower polishing rate than the second portion, and And carrying out chemical mechanical polishing on the isolation material layer and stopping at the patterned first hard mask layer.
  2. 2. The method of fabricating a semiconductor structure of claim 1, wherein the method of annealing the first portion comprises: forming a second hard mask material layer on the isolation material layer; Patterning the second hard mask material layer to form a patterned second hard mask layer, the patterned second hard mask layer covering the second portion and exposing the first portion, and And selectively annealing the isolation material layer of the first part by adopting a laser annealing mode.
  3. 3. The method of fabricating a semiconductor structure as recited in claim 2, wherein, and the mask plate used for carrying out the patterning treatment on the second hard mask material layer is the same as the mask plate used for forming the groove.
  4. 4. The method of fabricating a semiconductor structure of claim 1, wherein the method of annealing the first portion comprises: providing a laser annealing mask covering the second portion and exposing the first portion, and And under the shielding of the laser annealing photomask, selectively annealing the isolation material layer of the first part in a laser annealing mode.
  5. 5. The method of fabricating a semiconductor structure according to claim 2 or 4, wherein the isolating material layer on top of the first portion is annealed by means of laser annealing.
  6. 6. The method of fabricating a semiconductor structure of claim 1, wherein the intermediate structure comprises a semiconductor substrate, the trench being located in the semiconductor substrate.
  7. 7. The method of fabricating a semiconductor structure of claim 6, wherein the method of providing an intermediate structure comprises: Generating a first hard mask material layer on a semiconductor substrate, wherein the first hard mask material layer covers the top surface of the semiconductor substrate; patterning the first hard mask material layer to form a patterned first hard mask layer, and And etching the semiconductor substrate by taking the patterned first hard mask layer as a mask to form a plurality of grooves, wherein the plurality of grooves define a plurality of fins.
  8. 8. The method of fabricating a semiconductor structure of claim 7, wherein the second portion is directly above the fin.
  9. 9. The method of manufacturing a semiconductor structure of claim 1, wherein the intermediate structure comprises a semiconductor substrate and a first material layer on the semiconductor substrate, the trench being in the first material layer.
  10. 10. The method of manufacturing a semiconductor structure according to claim 1, wherein the top surface of the intermediate structure has a plurality of trenches, the pattern of the top surface of the intermediate structure is defined by the plurality of trenches, the intermediate structure includes a pattern-dense region and a pattern-sparse region, and the area of all the first portions of the pattern-dense region is smaller than the area of all the first portions of the pattern-sparse region in a unit area.

Description

Method for manufacturing semiconductor structure Technical Field The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor structure. Background In the field of semiconductor technology, chemical Mechanical Polishing (CMP) is a global planarization technique, and has a problem of being sensitive to patterns. Dishing (Dishing) of the cmp is caused by the different removal rates of the different regions, the region of loose pattern is easier to form dishing than the region of dense pattern, and the more loose pattern, the greater the depth of dishing may be. Fig. 1 to 3 are process diagrams illustrating a conventional method for fabricating a semiconductor structure. The method for fabricating the semiconductor structure includes the steps of forming a hard mask layer 13 on a semiconductor substrate 10 as shown in fig. 1, etching the hard mask layer 13 and the semiconductor substrate 10 to form a plurality of shallow trenches 11 in the semiconductor substrate 10, the plurality of shallow trenches 11 defining a plurality of fins (Fin), forming an isolation material layer 12 on the semiconductor substrate 10 as shown in fig. 2, the isolation material layer 12 covering the hard mask layer 13 and filling the plurality of shallow trenches 11, and performing chemical mechanical polishing on the isolation material layer 12 and stopping on the hard mask layer 13 as shown in fig. 3. For chemical mechanical polishing of Shallow Trench Isolation (STI), as shown in fig. 3, after chemical mechanical polishing, a larger dishing is easily present on the isolation material layer remained in the pattern sparse region II relative to the pattern dense region I, and excessive dishing may cause subsequent chemical mechanical polishing of polysilicon (Poly) and chemical mechanical polishing of interlayer dielectric (ILD) to risk residue in dishing region. In order to control dishing generated by chemical mechanical polishing, the overpolish time after polishing to the surface of the hard mask layer 13 should not be too long, but too short overpolish time is liable to cause the residual isolation material on the fin. The chemical mechanical polishing Process of Shallow Trench Isolation (STI) has a small Process window. Disclosure of Invention One of the objectives of the present invention is to provide a method for manufacturing a semiconductor structure, which can improve the dishing problem in the chemical mechanical polishing, expand the process window of the chemical mechanical polishing, and especially improve the problem that the pattern sparse region is prone to generate deeper dishing in the chemical mechanical polishing. In order to achieve the above purpose, the manufacturing method of the semiconductor structure comprises the steps of providing an intermediate structure, wherein a groove is formed in the top surface of the intermediate structure, a patterned first hard mask layer is arranged on the intermediate structure, covers the intermediate structure on the side edge of the groove and exposes the groove, an isolation material layer is generated on the intermediate structure, covers the top surface of the intermediate structure and fills the groove, the isolation material layer comprises a first part and a second part, the first part is located right above the groove, the second part is not annealed, the polishing rate of the isolation material layer of the first part is smaller than that of the isolation material layer of the second part, and the isolation material layer is subjected to chemical mechanical polishing and stops at the patterned first hard mask layer. Optionally, the method for annealing the first part comprises the steps of forming a second hard mask material layer on the isolation material layer, carrying out patterning treatment on the second hard mask material layer to form a patterned second hard mask layer, wherein the patterned second hard mask layer covers the second part and exposes the first part, and selectively annealing the isolation material layer of the first part in a laser annealing mode. Optionally, a mask plate used for performing the patterning treatment on the second hard mask material layer is the same as a mask plate used for forming the trench. Optionally, the method for annealing the first part comprises the steps of providing a laser annealing photomask, wherein the laser annealing photomask covers the second part and exposes the first part, and selectively annealing the isolation material layer of the first part in a laser annealing mode under the shielding of the laser annealing photomask. Optionally, annealing the isolation material layer on top of the first portion by means of laser annealing. Optionally, the intermediate structure includes a semiconductor substrate, and the trench is located in the semiconductor substrate. Optionally, the method for providing the intermediate structure comprises the steps of