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CN-121985754-A - Method for manufacturing semiconductor device, thermosetting resin composition, and die-cut and die-bonded integrated film

CN121985754ACN 121985754 ACN121985754 ACN 121985754ACN-121985754-A

Abstract

The invention relates to a method for manufacturing a semiconductor device, a thermosetting resin composition, and a die-cut and die-bonded integrated film. A method for manufacturing a semiconductor device according to one aspect of the present invention includes a step of preparing a die-cut and die-bonded integrated film including an adhesive layer formed of a thermosetting resin composition having a melt viscosity of 3100 Pa.s or more at 120 ℃, a pressure-sensitive adhesive layer and a base film, a step of bonding a surface of the die-cut and die-bonded integrated film on an adhesive layer side to a semiconductor wafer, a step of dicing the semiconductor wafer, a step of obtaining a semiconductor element with an adhesive by expanding the base film, a step of picking up the semiconductor element with an adhesive from the pressure-sensitive adhesive layer, a step of laminating the semiconductor element on another semiconductor element via the adhesive, and a step of thermally curing the adhesive.

Inventors

  • YAMAMOTO KAZUHIRO
  • Guo Tuyouyi
  • FUJIO SHUNSUKE

Assignees

  • 株式会社力森诺科

Dates

Publication Date
20260505
Application Date
20190710
Priority Date
20180711

Claims (16)

  1. 1. A method of manufacturing a semiconductor device, comprising: Preparing a die-cut and die-bonded integrated film comprising, in order, an adhesive layer, a pressure-sensitive adhesive layer, and a base film, wherein the adhesive layer is formed from a thermosetting resin composition having a melt viscosity of 3100 Pa.s or more at 120 ℃; bonding the surface of the die-cut and die-bonded integrated film on the adhesive layer side to a semiconductor wafer; Dicing the semiconductor wafer; a step of expanding the base film to obtain an adhesive-equipped semiconductor element obtained by singulating the semiconductor wafer and the adhesive layer; picking up the semiconductor element with adhesive from the pressure-sensitive adhesive layer; a step of laminating the adhesive-equipped semiconductor element on other semiconductor elements via the adhesive of the adhesive-equipped semiconductor element, and A step of thermally curing the adhesive, Wherein the thermosetting resin composition contains a thermosetting resin, a high molecular weight component having a molecular weight of 10 to 100 tens of thousands, and a filler, and the content of the thermosetting resin is 5 to 30 mass% and the content of the high molecular weight component is 30 to 66 mass% based on the total mass of the thermosetting resin composition, The plurality of semiconductor elements are stacked at laterally offset positions.
  2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein, The storage modulus of the thermosetting resin composition at 35 ℃ is 80-450 MPa.
  3. 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The melt viscosity of the thermosetting resin composition at 120 ℃ is 13000 Pa.s or more.
  4. 4. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The content of the high molecular weight component is 30 to 60 parts by mass relative to 100 parts by mass of the total mass of the thermosetting resin, the high molecular weight component and the filler.
  5. 5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The filler is contained in an amount of 25 to 45 mass% based on the total mass of the thermosetting resin composition.
  6. 6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein, The semiconductor wafer is singulated by one of stealth dicing and blade dicing, and the substrate film is expanded under cooling.
  7. 7. The manufacturing method of a semiconductor device according to claim 1 or 2, which is a method of manufacturing a three-dimensional NAND-type memory.
  8. 8. A thermosetting resin composition for use in a process for manufacturing a semiconductor device, The melt viscosity of the thermosetting resin composition at 120 ℃ is 3100 Pa.s or more, The thermosetting resin composition contains a thermosetting resin, a high molecular weight component with a molecular weight of 10-100 ten thousand and a filler, wherein the content of the thermosetting resin is 5-30% by mass and the content of the high molecular weight component is 30-66% by mass based on the total mass of the thermosetting resin composition.
  9. 9. The thermosetting resin composition according to claim 8, which has a storage modulus at 35 ℃ of 80 MPa to 450MPa.
  10. 10. The thermosetting resin composition according to claim 8 or 9, which has a melt viscosity of 13000 Pa-s or more at 120 ℃.
  11. 11. The thermosetting resin composition according to claim 8 or 9, wherein, The content of the high molecular weight component is 30 to 60 parts by mass relative to 100 parts by mass of the total mass of the thermosetting resin, the high molecular weight component and the filler.
  12. 12. The thermosetting resin composition according to claim 8 or 9, wherein, The filler is contained in an amount of 25 to 45 mass% based on the total mass of the thermosetting resin composition.
  13. 13. The thermosetting resin composition according to claim 8 or 9, which is used in a process for manufacturing a three-dimensional NAND-type memory.
  14. 14. The thermosetting resin composition according to claim 8 or 9, which is used in the method for manufacturing a semiconductor device according to any one of claims 1 to 7.
  15. 15. A die-cut and die-bonded integrated film comprising: pressure-sensitive adhesive layer, and An adhesive layer formed of the thermosetting resin composition of any one of claims 8 to 14.
  16. 16. The die-cut and die-bonded integral film according to claim 15, wherein, The thickness of the adhesive layer is 3-40 mu m.

Description

Method for manufacturing semiconductor device, thermosetting resin composition, and die-cut and die-bonded integrated film The present application is a divisional application of the application date of 2019, 7/10, the priority date of 2018, 7/11, chinese patent application number 201980045678.2, entitled "method for manufacturing semiconductor device, thermosetting resin composition, die-cut and die-bonded film". Technical Field The invention relates to a method for manufacturing a semiconductor device, a thermosetting resin composition, and a die-cut and die-bonded integrated film. Background The semiconductor device is manufactured through the following steps. First, a semiconductor wafer is fixed by a pressure-sensitive adhesive sheet for dicing (pressure-SENSITIVE ADHESIVE SHEET), and in this state, the semiconductor wafer is singulated into semiconductor chips. Thereafter, an expanding (expanding) process, a pick up (pick up) process, a die bonding (die bonding) process, a reflow (reflow) process, a die bonding (die bonding) process, and the like are performed. One of important characteristics required for a semiconductor device is connection reliability. In order to improve connection reliability, a film-like adhesive (adhesive) for die bonding has been developed in consideration of characteristics such as heat resistance, moisture resistance, and reflow resistance. For example, patent document 1 discloses an adhesive sheet containing a resin and a filler, wherein the resin contains a high molecular weight component and a thermosetting component mainly composed of an epoxy resin. Technical literature of the prior art Patent literature Patent document 1 Japanese patent laid-open publication 2016-190964 Disclosure of Invention Technical problem to be solved by the invention The present inventors have made developments of thermosetting adhesives used in a process for manufacturing a semiconductor device (for example, a three-dimensional NAND memory) having a high capacity by stacking semiconductor elements in a plurality of stages. The three-dimensional NAND wafer includes a complicated circuit layer and a thin semiconductor layer (for example, about 15 μm to 25 μm), and thus has a problem that semiconductor elements obtained by singulating the semiconductor layers are likely to warp. Fig. 5 (a) is a cross-sectional view schematically showing a structure in the manufacturing process of the semiconductor device. The structure 30 shown in fig. 5 (a) includes a substrate 10, and four semiconductor elements S1, S2, S3, and S4 stacked on the substrate 10. For connection to an electrode (not shown) formed on the surface of the substrate 10, four semiconductor elements S1, S2, S3, and S4 are stacked at positions offset from each other in the lateral direction (direction orthogonal to the stacking direction) (see fig. 1). The semiconductor element S1 is adhered to the substrate 10 by an adhesive, and the adhesive is present among the three semiconductor elements S2, S3, and S4. According to the studies of the present inventors, when the semiconductor element S1, the semiconductor element S2, the semiconductor element S3, and the semiconductor element S4 each have a complicated circuit layer (upper surface side) and a thin semiconductor layer (lower surface side), separation is likely to occur between the semiconductor element S1 in the first stage and the semiconductor element S2 in the second stage as shown in fig. 5 (b). For this reason, the present inventors speculate as follows. As described above, the semiconductor elements S1, S2, S3, and S4 have a property of being easily warped (warp stress) due to the complicated circuit layer and the thin semiconductor layer. The overhang portion H is formed by stacking a plurality of semiconductor elements at laterally offset positions. It was confirmed that peeling does not occur in the stage of mounting the semiconductor element S2 in the second stage, and therefore, by mounting the semiconductor element S3 in the third stage and the semiconductor element S4 in the fourth stage, the upward force (the warp stress in the direction of peeling from the semiconductor element S1 in the first stage) increases in the overhang H of the semiconductor element S2 in the second stage. The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a method for manufacturing a semiconductor device in which a plurality of semiconductor elements are stacked, and peeling between adjacent semiconductor elements is less likely to occur. The present invention also provides a thermosetting resin composition and a die-cut and die-bonded film which can be suitably used in the production method. Means for solving the technical problems An aspect of the present invention provides a method for manufacturing a semiconductor device (for example, a three-dimensional NAND-type memory) in which a plurality of semiconductor elements