CN-121985788-A - Gate stress test method, device, equipment and medium of power semiconductor device

CN121985788ACN 121985788 ACN121985788 ACN 121985788ACN-121985788-A

Abstract

The invention discloses a method, a device, equipment and a medium for testing gate stress of a power semiconductor device. The method comprises the steps of obtaining a power semiconductor device to be tested, electrically shorting a drain electrode and a source electrode of the power semiconductor device to be tested, applying a gate source stress voltage pulse higher than rated working gate voltage between a gate electrode and the source electrode of the power semiconductor device to be tested, measuring gate leakage current of the power semiconductor device to be tested under preset gate voltage after the gate source stress voltage pulse is applied, comparing a measured value of the gate leakage current with a preset threshold value, and screening out the power semiconductor device with potential defects of the gate according to a comparison result. The invention effectively screens the semiconductor power device with potential defect problem of the grid.

Inventors

WANG GUIZHOU
CHEN XIN
Yu Shuangbai

Assignees

基本半导体(无锡)有限公司

Dates

Publication Date: 20260505
Application Date: 20251230

Claims (10)

1. A gate stress test method of a power semiconductor device, comprising: Acquiring a power semiconductor device to be tested, and electrically shorting a drain electrode and a source electrode of the power semiconductor device to be tested; applying a gate-source stress voltage pulse higher than a rated working gate voltage between a gate and a source of the power semiconductor device to be tested; measuring the grid leakage current of the power semiconductor device to be tested under the preset grid voltage after the grid source stress voltage pulse is applied; and comparing the measured value of the gate leakage current with a preset threshold value, and screening out the power semiconductor device with potential defects of the gate according to the comparison result.
2. The method for testing gate stress of a power semiconductor device according to claim 1, wherein the obtaining the power semiconductor device to be tested, electrically shorting the drain and the source of the power semiconductor device to be tested, comprises: and acquiring test equipment for testing the power semiconductor device to be tested, controlling a relay matrix in the test equipment, and closing a switch channel corresponding to the drain electrode and the source electrode of the power semiconductor device to be tested.
3. The method of gate stress testing of a power semiconductor device according to claim 1, wherein applying a gate-source stress voltage pulse higher than a rated operating gate voltage between a gate and a source of the power semiconductor device to be tested comprises: acquiring a voltage source of test equipment, connecting an anode of the voltage source of the test equipment to a grid electrode of a power semiconductor device to be tested, and connecting a cathode of the voltage source of the test equipment to a source electrode of the power semiconductor device to be tested; and controlling the voltage source of the testing equipment to output a grid source stress voltage pulse higher than the rated working grid voltage to a position between the grid electrode and the source electrode of the power semiconductor device to be tested.
4. A method of gate stress testing of a power semiconductor device according to claim 3, wherein controlling the voltage source of the test apparatus to output a gate-source stress voltage pulse above a nominal operating gate voltage between the gate and source of the power semiconductor device to be tested comprises: and controlling the grid source stress voltage pulse output by the voltage source of the testing equipment to be higher than the rated working grid voltage of the power semiconductor device to be tested and not to exceed a preset first safety voltage value.
5. The method of gate stress testing of a power semiconductor device according to claim 4, wherein the controlling the voltage source of the testing apparatus outputs gate-source stress voltage pulses between the gate and the source of the power semiconductor device to be tested, further comprising And controlling the rising time and the falling time of the gate-source stress voltage pulse output by the voltage source of the test equipment to be smaller than a first preset time threshold value, and controlling the holding time of the gate-source stress voltage pulse output by the voltage source of the test equipment to be smaller than a second preset time threshold value.
6. The method for testing gate stress of a power semiconductor device according to claim 1, wherein the comparing the measured value of the gate leakage current with a preset threshold value, and screening the power semiconductor device with the potential defect of the gate, comprises: recording a gate leakage current value of the power semiconductor device to be tested after the gate-source stress voltage pulse is applied; Comparing the grid leakage current value of the power semiconductor device to be tested with a preset qualified threshold value of the grid leakage current value; and marking the power semiconductor device to be tested, of which the gate leakage current value exceeds the qualified threshold value, as a defective product according to the comparison result.
7. The method for testing gate stress of a power semiconductor device according to claim 1, wherein after applying a gate-source stress voltage pulse higher than a rated operation gate voltage between a gate and a source of the power semiconductor device to be tested, the method further comprises: and controlling the time interval between the application ending time of the gate source stress voltage pulse and the measurement starting time of the gate leakage current of the power semiconductor device to be tested to be smaller than a third preset time threshold.
8. A gate stress testing apparatus of a power semiconductor device, comprising: The device comprises an acquisition module, a power semiconductor device testing module and a power semiconductor device testing module, wherein the acquisition module is used for acquiring a power semiconductor device to be tested and electrically shorting a drain electrode and a source electrode of the power semiconductor device to be tested; the pressurizing module is used for applying a gate-source stress voltage pulse higher than the rated working gate voltage between the gate and the source of the power semiconductor device to be tested; The measuring module is used for measuring the grid leakage current of the power semiconductor device to be tested under the preset grid voltage after the grid source stress voltage pulse is applied; And the comparison module is used for comparing the measured value of the gate leakage current with a preset threshold value and screening out the power semiconductor device with the potential defect of the gate according to the comparison result.
9. A gate stress test apparatus for a power semiconductor device, comprising a memory and a processor, wherein: The memory is used for storing a computer program; The processor is configured to read the computer program in the memory and execute the steps of the method for testing gate stress of a power semiconductor device according to any one of claims 1 to 7.
10. A computer readable storage medium, characterized in that a readable computer program is stored thereon, which program, when being executed by a processor, implements the steps of a method for gate stress testing of a power semiconductor device according to any of claims 1-7.

Description

Gate stress test method, device, equipment and medium of power semiconductor device Technical Field The invention relates to the technical field of semiconductors, in particular to a method, a device, equipment and a medium for testing gate stress of a power semiconductor device. Background The power semiconductor device has become a core component of high-end power electronic equipment such as new energy automobiles, rail transit, smart grids and the like by virtue of excellent characteristics such as high frequency, high voltage resistance, high temperature working capacity, low loss and the like. However, the gate oxide reliability of a power semiconductor device is one of the key factors affecting its long-term stability. During fabrication, potential defects may be introduced that cause localized thinning or weak spots in the gate oxide due to epitaxial defects, process contamination, or stress non-uniformity. Such defects may appear normal under conventional testing, but in long-term high-voltage and high-temperature operating environments, early failure of the gate of the power semiconductor device is extremely easy to occur, and the reliability of the end product is seriously affected. In order to ensure the product quality, the current industry mainly relies on the reliability checking procedure at the rear end of the production test flow to screen potential defects of weak points of the oxide layer, and the potential defects mainly comprise a high-temperature reverse bias test and a reactive aging test. However, high temperature reverse bias testing is inefficient, limiting throughput. The process accelerates the occurrence of internal potential failure by utilizing the synergistic effect of electrothermal stress by applying high temperature and high gate bias voltage to the power semiconductor device. Although this method is effective in defect screening, the test period is extremely long, typically lasting from hours to days. The reactive power aging test procedure is to continuously operate the power semiconductor device for a long time and continuously monitor the reactive power change, so as to indirectly screen out the power semiconductor device with potential defect problem of the grid electrode. In addition, in the normal temperature or high temperature static state testing procedure, the lack of effective grid instant overvoltage test can not effectively screen out the power semiconductor device with the potential defect problem of the grid, and bad products can flow into the next testing procedure or be directly packaged and shipped. Therefore, how to effectively screen out the semiconductor power device with the potential defect problem of the grid is a technical problem to be solved. Disclosure of Invention The invention provides a method, a device, equipment and a medium for testing gate stress of a power semiconductor device, which are used for solving the technical problem of how to effectively screen out a semiconductor power device with potential defect problem of a gate. In order to solve the above technical problem, in a first aspect, the present invention provides a method for testing gate stress of a power semiconductor device, the method comprising: Acquiring a power semiconductor device to be tested, and electrically shorting a drain electrode and a source electrode of the power semiconductor device to be tested; applying a gate-source stress voltage pulse higher than a rated working gate voltage between a gate and a source of the power semiconductor device to be tested; measuring the grid leakage current of the power semiconductor device to be tested under the preset grid voltage after the grid source stress voltage pulse is applied; and comparing the measured value of the gate leakage current with a preset threshold value, and screening out the power semiconductor device with potential defects of the gate according to the comparison result. Optionally, the obtaining the power semiconductor device to be tested, electrically shorting the drain and the source of the power semiconductor device to be tested, includes: and acquiring test equipment for testing the power semiconductor device to be tested, controlling a relay matrix in the test equipment, and closing a switch channel corresponding to the drain electrode and the source electrode of the power semiconductor device to be tested. Optionally, the applying a gate-source stress voltage pulse higher than the rated operation gate voltage between the gate and the source of the power semiconductor device to be tested includes: acquiring a voltage source of test equipment, connecting an anode of the voltage source of the test equipment to a grid electrode of a power semiconductor device to be tested, and connecting a cathode of the voltage source of the test equipment to a source electrode of the power semiconductor device to be tested; and controlling the voltage source of the testing equipment to output a grid source stress v