CN-121985792-A - Method for manufacturing semiconductor structure

Abstract

The disclosure provides a manufacturing method of a semiconductor structure, which relates to the technical field of semiconductors, and comprises the steps of providing a substrate structure, forming a mask layer on the substrate structure, wherein the mask layer is provided with an initial pattern corresponding to a target pattern, the initial pattern comprises one or more groups of second patterns, each group of second patterns comprises one or more initial openings which are arranged at intervals in a first direction, and performing first anisotropic etching on the mask layer, so that the size of each initial opening in the first direction is increased to form a corresponding sub-pattern, and the initial pattern is changed into the target pattern.

Inventors

• ZHOU YONGJIAN
• Request for anonymity
• Fu tengfei
• ZHANG RIQING

Assignees

• 深圳市鹏芯微集成电路制造有限公司

Dates

Publication Date

20260505

Application Date

20241029

Claims (12)

1. 1. A method of fabricating a semiconductor structure, comprising: providing a substrate structure; forming a mask layer on the substrate structure, the mask layer having an initial pattern corresponding to a target pattern, wherein: The target pattern includes one or more sets of first patterns, each set of first patterns including a plurality of target openings arranged at intervals in a first direction, each set of first patterns being divided into one or more sub-patterns, each sub-pattern including one target opening or at least two target openings in succession, In each group of first patterns divided into a plurality of sub patterns, the pitch between two adjacent sub patterns is equal to or greater than a first threshold, In a first sub-pattern including at least two consecutive target openings, adjacent target openings satisfy a first condition that a pitch between adjacent target openings is smaller than a second threshold value or a second condition that a pitch between adjacent target openings is equal to or larger than the second threshold value and a size of at least one of adjacent target openings in the first direction is equal to or smaller than a preset size, the second threshold value is not larger than the first threshold value, The initial pattern includes one or more groups of second patterns corresponding to the one or more groups of first patterns, each group of second patterns includes one or more initial openings arranged at intervals in the first direction, each initial opening corresponds to one sub-pattern of the group of first patterns corresponding to the group of second patterns where the initial opening is located, the initial openings corresponding to the first sub-patterns are separated by a spacer in the first direction, and A first anisotropic etch is performed on the mask layer such that a size of each initial opening in the first direction is increased to form a corresponding sub-pattern, thereby changing the initial pattern into the target pattern.
2. 2. The method of claim 1, wherein, Two adjacent second patterns in the initial patterns comprise a first second pattern and a second pattern, and each initial opening in the first second pattern is not overlapped with each initial opening in the second pattern in the first direction.
3. 3. The method of claim 2, wherein, Any two adjacent second patterns in the initial pattern comprise the first second pattern and the second pattern.
4. 4. The method of claim 1, wherein the substrate structure comprises a dielectric layer, the mask layer being formed over the dielectric layer, the method further comprising: Etching the dielectric layer with the mask layer as a mask after performing the first anisotropic etching to transfer each target opening in the target pattern into the dielectric layer, and And filling a metal material in each target opening in the dielectric layer.
5. 5. The method of claim 4, wherein the substrate structure further comprises: A substrate; A gate structure on the substrate, and Electrode regions located on both sides of the gate structure; wherein the dielectric layer covers the gate structure and the electrode region, and the metal material contacts the electrode region to form a contact.
6. 6. The method of claim 5, wherein, The substrate structure further comprises a fin on the substrate, the gate structure spans the fin, the electrode region is located on the fin, and the dielectric layer further covers the fin.
7. 7. The method of claim 4, further comprising: A second anisotropic etch is performed on the dielectric layer prior to filling the metal material such that each target opening in the dielectric layer increases in size in the first direction.
8. 8. The method according to any one of claims 1-7, wherein, In the second condition, a size of each of the adjacent target openings in the first direction is equal to or smaller than the preset size.
9. 9. The method according to any one of claims 1-7, wherein, The preset size is a limit size of a photolithography process for forming the initial pattern.
10. 10. The method according to any one of claims 1-7, wherein, The size of each sub-pattern in the first direction is larger than the preset size.
11. 11. The method according to any one of claims 1-7, wherein, The first threshold is equal to the second threshold.
12. 12. The method according to any one of claims 1-7, wherein, The first anisotropic etch is an ion beam etch.

Description

Method for manufacturing semiconductor structure Technical Field The present disclosure relates to the field of semiconductor technology, and in particular, to a method for manufacturing a semiconductor structure. Background With the shrinking critical dimensions of integrated circuits, the process requirements for forming a particular pattern, particularly one comprising a plurality of closely spaced patterns, are increasing. In the related art, photolithography cutting and/or multiple exposure are used to form more complex specific patterns. Disclosure of Invention According to an aspect of the disclosed embodiments, a method for manufacturing a semiconductor structure is provided, the method includes providing a substrate structure, forming a mask layer on the substrate structure, the mask layer having an initial pattern corresponding to a target pattern, wherein the target pattern includes one or more sets of first patterns, each set of first patterns includes a plurality of target openings arranged at intervals in a first direction, each set of first patterns is divided into one or more sub-patterns, each sub-pattern includes one target opening or two continuous target openings, a spacing between two adjacent sub-patterns is equal to or greater than a first threshold value in each set of first patterns divided into a plurality of sub-patterns, the adjacent target openings satisfy a first condition or a second condition in a first sub-pattern including at least two continuous target openings, the first condition is that a spacing between adjacent target openings is smaller than a first threshold value, the second condition is that a spacing between adjacent target openings is equal to or greater than the second threshold value, and at least one of the adjacent target openings is not equal to the first threshold value, etching a first set of first pattern is not equal to or greater than the first threshold value in the first direction, a first pattern is performed in a first sub-pattern including a first pattern having a first set of initial pattern, the first pattern is not equal to or greater than a first threshold value, the first pattern is aligned to the first pattern is greater than a first threshold value, the size of each initial opening in the first direction is increased to form a corresponding sub-pattern, thereby changing the initial pattern into the target pattern. According to some embodiments of the present disclosure, the two adjacent sets of second patterns in the initial pattern include a first set of second patterns and a second set of second patterns, each initial opening in the first set of second patterns and each initial opening in the second set of second patterns are non-overlapping in the first direction. According to some embodiments of the disclosure, any two adjacent sets of second patterns in the initial pattern each include the first set of second patterns and the second set of second patterns. According to some embodiments of the present disclosure, the substrate structure includes a dielectric layer over which the mask layer is formed, the method further including etching the dielectric layer with the mask layer as a mask to transfer each of the target openings in the target pattern into the dielectric layer after performing the first anisotropic etch, and filling a metal material in each of the target openings in the dielectric layer. According to some embodiments of the present disclosure, the substrate structure further comprises a substrate, a gate structure on the substrate, and electrode regions on both sides of the gate structure, wherein the dielectric layer covers the gate structure and the electrode regions, and the metal material contacts the electrode regions to form contacts. According to some embodiments of the present disclosure, the substrate structure further comprises a fin on the substrate, the gate structure spans the fin, the electrode region is located on the fin, and the dielectric layer further covers the fin. According to some embodiments of the present disclosure, a second anisotropic etch is performed on the dielectric layer prior to filling the metal material such that each target opening in the dielectric layer increases in size in the first direction. According to some embodiments of the disclosure, in the second condition, a size of each of the adjacent target openings in the first direction is equal to or smaller than the preset size. According to some embodiments of the disclosure, the preset dimension is a limit dimension of a photolithography process forming the initial pattern. According to some embodiments of the disclosure, a dimension of each sub-pattern in the first direction is greater than the preset dimension. According to some embodiments of the disclosure, the first threshold is equal to the second threshold. According to some embodiments of the disclosure, the first anisotropic etch is an ion beam etch. Drawings The accompanyi