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CN-121985797-A - Method for improving stability of film thickness of bottom interlayer of groove between AIO etching products

CN121985797ACN 121985797 ACN121985797 ACN 121985797ACN-121985797-A

Abstract

The invention discloses a method for improving the stability of the interlayer film thickness at the bottom of a groove between AIO etching products, which comprises the process of improving the film thickness between wafers in batches. The inter-wafer film thickness improvement process comprises AIO etching a batch of wafers in an etching chamber. First monitoring data of byproducts in the etching chamber and forming the byproducts are monitored in real time during AIO etching of each wafer. After the AIO etching of the current wafer is finished, the WAC condition is optimized according to the first monitoring data, and then WAC is carried out on the etching cavity according to the optimized WAC condition. Thereafter, AIO etching of the wafer of the next wafer is performed. The invention can improve the stability of the thickness of the interlayer film at the bottom of the groove of the AIO etching product.

Inventors

  • HU WEILING

Assignees

  • 上海华力集成电路制造有限公司

Dates

Publication Date
20260505
Application Date
20260130

Claims (14)

  1. 1. A method for improving the film thickness stability of a bottom interlayer of a groove between AIO etched products is characterized by comprising the steps of carrying out a process for improving the film thickness between wafers in a batch; The inter-wafer film thickness improvement process in the batch comprises the following steps: AIO etching is carried out on the corresponding wafers in a batch in the etching cavity; monitoring byproducts in the etching cavity in real time during the AIO etching process of the wafer and forming first monitoring data of the byproducts; After the AIO of the wafer is etched, optimizing WAC conditions according to the first monitoring data, and then carrying out WAC on the etching cavity according to the optimized WAC conditions; Thereafter, the AIO etching of the wafer of the next wafer of the same lot is performed.
  2. 2. The method for improving interlayer film thickness stability of a trench bottom between AIO etched products as set forth in claim 1, wherein said real-time monitoring is accomplished by an OES window system.
  3. 3. The method for improving interlayer film thickness stability at the bottom of a trench between AIO etched products as set forth in claim 1, wherein optimizing said WAC conditions comprises optimizing an over-etch of said WAC.
  4. 4. The method of claim 1, wherein the maximum number of wafers in a batch is 25 and are placed in the same wafer cassette.
  5. 5. The method for improving the interlayer film thickness stability of the bottom of a trench between AIO etched products according to claim 1, wherein the process conditions of the AIO etching in the same etching chamber are the same; The products of the wafers in the same batch are the same; Different batches of the wafer have the same or different products; classifying the products according to the number of bare chips and the light transmittance, and taking the products with the number of bare chips larger than or equal to a first target or the light transmittance larger than or equal to a second target as first-class products; the first type of product performs the inter-wafer film thickness improvement process within the batch.
  6. 6. The method of claim 5, wherein the product having the number of bare dies smaller than a first target or the transmittance smaller than a second target is used as a second type of product, and the second type of product is used or is not used for the inter-wafer film thickness improvement process in the batch.
  7. 7. The method for improving interlayer film thickness stability at the bottom of an inter-trench in an AIO etched product as defined in claim 6, further comprising performing an inter-batch film thickness improvement process; The process for improving the film thickness between batches comprises the following steps: classifying each product which enters the same etching cavity for mixed running, wherein the products are at least divided into a first type of product and a second type of product; setting a first type of aging etching process corresponding to the first type of product, wherein the first type of aging etching process is set according to the requirements of the cavity environment during AIO etching of the second type of product; Sequentially carrying out the AIO etching on each batch of wafers, and triggering and carrying out the first aging etching process when the first type of products are finished and the wafers of the next batch are the second type of products so as to enable the intracavity environment of the etching cavity to be consistent with the intracavity environment of the AIO etching of the second type of products; and after the first aging etching process is completed, carrying out AIO etching of the wafers of the next batch.
  8. 8. The method of claim 7, wherein the AIO etching process is not triggered and the AIO etching of the next lot of wafers is directly performed when the second lot of wafers remain as the second lot of wafers after the second lot of wafers are completed.
  9. 9. The method of claim 7, wherein when the second type of product is completed and the next lot of wafers are the first type of product, the first type of seasoning etching process is not triggered and the AIO etching of the next lot of wafers is directly performed.
  10. 10. The method of claim 7, wherein when the first type of product is completed and the next lot of wafers are the first type of product, the first type of seasoning etching process is not triggered and the AIO etching of the next lot of wafers is directly performed.
  11. 11. The method for improving interlayer film thickness stability at the bottom of a trench between AIO etched products of claim 1, wherein said AIO etching is used for etching said interlayer film on said wafer to form a trench and a via opening at the bottom of a portion of said trench at the same time; The trench bottom interlayer film is the interlayer film at the trench bottom outside the via opening.
  12. 12. The method for improving interlayer film thickness stability at the bottom of a trench between AIO etched products according to claim 11, wherein: the material of the interlayer film includes a low dielectric constant material.
  13. 13. The method for improving interlayer film thickness stability at the bottom of a trench between AIO etched products according to claim 12, wherein: the low dielectric constant material includes SiCOH.
  14. 14. The method of claim 12, wherein a first NDC layer and a TEOS layer are further formed on the bottom of the interlayer film, and a bottom interlayer film and a bottom metal layer are formed on the bottom of the first NDC layer; A second NDC layer, NFDARC layers and a TiN metal hard mask layer are also formed on top of the interlayer film.

Description

Method for improving stability of film thickness of bottom interlayer of groove between AIO etching products Technical Field The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for improving the stability of the thickness of an interlayer film at the bottom of a groove between integrated in one (AIO) etched products. Background At present, in the large-scale wafer manufacturing process, the products are diversified and are more in different technical platforms, AIO etching is adopted in the post Duan Dama leather technology, and the AIO platforms are classified according to cavities due to different etching films, fillers and line widths. However, in the same platform, such as light transmittance and difference of the number (Count) of bare chips (DIE), these two parameters are critical (key) parameters for etching (etc), the etching area of the product with high light transmittance and multiple DIE is large, the byproducts in the cavity, i.e. polymers (polymers), are heavy, the thickness of the Low dielectric constant remainder (Low K domain) between wafers (WTW) tends to rise (trend up), when the next Low light transmittance or small DIE is followed by the next product, the first wafers in WTW are affected by AIO etching of the previous batch (lot) of products, the heavy phenomenon of polymers is not completely counteracted, the Low K domain is also high, and the process of cleaning such as WLDC CLEAN tends to be stable. The trench is filled with Cu after AIO etching, and the thickness of Cu has a strong correlation with WAT RS, so that the thickness of Low K domain after ETCH directly affects the final Cu thickness after Electroplating (ECP) Cu filling and CMP grinding. As shown in fig. 1, which is a schematic view of a device structure in conventional AIO etching, AIO etching is used to etch the interlayer film 105 on the wafer to form a trench 109 and a via opening 110 at the same time, where the via opening 110 is located at the bottom of a portion of the trench 109. As shown by the circle 111, the trench bottom interlayer film is the interlayer film 105 located at the bottom of the trench 109 outside the via opening 110. The material of the interlayer film 105 includes a low dielectric constant material. The low dielectric constant material includes SiCOH. Wherein black diamond II (BDII) is also a SiCOH material. A first nitrogen doped silicon carbide (NDC) layer 103 and a TEOS layer 104 are also formed on the bottom of the interlayer film 105, and a bottom interlayer film 101 and a bottom metal layer 102 are formed on the bottom of the first NDC layer 103. A second NDC layer 106, a fluorine-free doped DARC (NFDARC) layer 107, and a TiN metal hard mask layer (MHM) 108 are also formed on top of the interlayer film 105. Typically, one etch chamber will perform AIO etching on multiple wafers, e.g., AIO etching on the same lot (lot) of wafers at the same time. However, when the transmittance is high or the DIE Count is large, the byproducts in the cavity are heavy, which affects the etching rate, such as decreasing the etching rate, so as the number of wafers to be processed increases, the byproducts in the cavity accumulate, so that the etching rate of the subsequent wafers gradually decreases, and thus the thickness of the interlayer film at the bottom of the trench, i.e., the interlayer film at the circle 111 in fig. 1, increases. As shown in FIG. 2, the curve 201 is a curve of the thickness of the bottom interlayer film of the trench after AIO etching is performed on each wafer in the same batch in the conventional etching chamber, the ordinate corresponds to the left coordinate, the broken line 202 is a fitting line of the curve 201, each data point on the curve 201 corresponds to the thickness of the bottom interlayer film of the trench measured on each wafer in the same batch, and it can be seen that the thickness of the bottom interlayer film of the trench gradually increases and increases to be larger than the target line indicated by the mark 203 as the number of wafers increases. Also shown in fig. 2 is the deposition thickness of the interlayer film, with the corresponding ordinate being the right ordinate. In addition to the effect on each wafer in the same lot, the AIO etching of wafers with high transmittance or large DIE Count can also have an adverse effect on the AIO etching of wafers with low transmittance or small DIE Count in the next lot when the wafers in the subsequent lot are low in transmittance or small DIE Count, mainly by-products accumulated in the chamber can reduce the etching rate of the preceding wafers in the next lot. As shown in FIG. 3, the curve 204 is a curve of the thickness of the bottom interlayer film of the trench after AIO etching is performed on a batch of wafers of a second product with small bare die number or low light transmittance after AIO etching is performed on a wafer of a first product wi