CN-121985800-A - Method for manufacturing semiconductor structure and semiconductor structure

CN121985800ACN 121985800 ACN121985800 ACN 121985800ACN-121985800-A

Abstract

The embodiment of the application provides a manufacturing method of a semiconductor structure and the semiconductor structure. The manufacturing method comprises the steps of providing a substrate, forming a first transfer layer on the substrate by adopting a first photoetching process, forming a side wall covering the side wall of the first transfer layer, forming an adjusting layer covering the side wall and the first transfer layer to meet the requirement that a first size is larger than or equal to a first preset value, wherein the first size is defined as the difference between the line spacing and the line width of the first transfer layer minus the line width of the side wall twice, the line width of the adjusting layer is positively correlated with the difference between the first size and the first preset value, removing the horizontal part of the adjusting layer and the first transfer layer by adopting a second photoetching process to form a second transfer layer, wherein the difference between the adjacent two line spacing of the second transfer layer is smaller than or equal to a second preset value, forming a groove in the substrate by taking the second transfer layer as a mask, and filling conductive materials in the groove to form an interconnection layer.

Inventors

LI FEI
DUAN CHENGWEN
GAO YAODONG

Assignees

深圳市鹏芯微集成电路制造有限公司

Dates

Publication Date: 20260505
Application Date: 20241028

Claims (10)

1. A method of fabricating a semiconductor structure, comprising: Providing a substrate; forming a first transfer layer on the substrate by adopting a first photoetching process; Forming a side wall covering the side wall of the first transfer layer; forming an adjusting layer covering the side wall and the first transfer layer to meet the condition that a first size is larger than or equal to a first preset value, wherein the first size is defined as the difference between the line distance and the line width of the first transfer layer minus twice the line width of the side wall; removing the horizontal part of the regulating layer and the first transfer layer by adopting a second photoetching process to form a second transfer layer, wherein the difference between two adjacent line distances of the second transfer layer is smaller than or equal to a second preset value; forming a groove in the substrate by taking the second transfer layer as a mask; and filling conductive materials in the grooves to form interconnection layers.
2. The method of claim 1, wherein forming the adjustment layer to cover the sidewall and the first transfer layer to meet a first dimension greater than or equal to a first predetermined value comprises: the line width of the formed regulating layer has a first width according to the difference between the first size and a first preset value belonging to a first interval, or According to the difference between the first size and the first preset value belonging to a second interval, the line width of the formed adjusting layer is provided with a second width; the first interval and the second interval are two different intervals in a plurality of continuous intervals, the value of the first interval is smaller than that of the second interval, and the first width is smaller than the second width.
3. The method of claim 1, wherein the second dimension comprises an absolute value of a difference between a line width of the sidewall and a line width of the adjustment layer that is twice less than a line width of the first transfer layer, and wherein a ratio between the second dimension and the line width of the adjustment layer ranges from 1.0 to 1.5.
4. The method of manufacturing of claim 1, wherein removing the horizontal portion of the adjustment layer and the first transfer layer using a second photolithographic etching process forms a second transfer layer, comprising: Forming a second patterned photoresist layer covering the adjustment layer; sequentially removing the adjusting layer and the first transfer layer which are positioned on the first transfer layer by taking the second patterning photoetching layer as a mask; removing the second patterned photoresist layer, and And removing the regulating layer on the substrate to form the second transfer layer, wherein the vertical part of the regulating layer which is not removed and the side wall form the second transfer layer.
5. The method of manufacturing of claim 4, wherein the vertical portion of the adjustment layer that is not removed covers the top surface of the sidewall and one sidewall.
6. The method according to claim 4, wherein, The providing a substrate includes: Sequentially forming a target layer and a first etching stop layer; Sequentially forming a hard mask layer and a second etching stop layer which cover the first etching stop layer; The forming a first transfer layer on the substrate using a first photolithographic etching process includes: Forming the first transfer layer on the second etch stop layer using the first photolithographic etching process; The forming a trench in the substrate using the second transfer layer as a mask includes: Etching the second etching stop layer and the hard mask layer by taking the second transfer layer as a mask to form a hard mask pattern; and etching the first etching stop layer and the target layer by taking the hard mask pattern as a mask to form the groove.
7. The method of manufacturing of claim 1, wherein forming a first transfer layer on the substrate using a first photolithographic etching process comprises: forming a first transfer material layer overlying the substrate; forming a first patterned photoresist layer overlying the first transfer material layer; And removing part of the first transfer material layer on the substrate by taking the first patterning photoetching layer as a mask to form the first transfer layer, wherein the first transfer material layer which is not removed forms the first transfer layer.
8. The method of manufacturing of claim 7, wherein forming the sidewall that covers the first transfer layer sidewall comprises: forming a side wall material layer covering the first transfer layer; And removing the horizontal part and part of the vertical part of the side wall material layer to form the side wall, wherein the vertical part of the side wall material layer which is not removed forms the side wall.
9. The method of manufacturing of claim 8, wherein the sidewall height is less than the first transfer layer height.
10. A semiconductor structure, comprising: A substrate including a transistor; source-drain contact connected to the source or drain of the transistor; The interconnection layer is obtained by the manufacturing method according to any one of claims 1-9, is located on the source-drain contact and is connected with the source-drain contact, or is located on a first metal interconnection layer, wherein the first metal interconnection layer is connected with the source-drain contact, the interconnection layer comprises a conductive through hole and a metal wire located on the conductive through hole, the conductive through hole is located on the first metal interconnection layer, and the metal wire is connected with the first metal interconnection layer through the conductive through hole.

Description

Method for manufacturing semiconductor structure and semiconductor structure Technical Field The present application relates to the field of semiconductor technology, and more particularly, to a method for manufacturing a semiconductor structure and a semiconductor structure. Background As semiconductor process dimensions shrink, the accuracy requirements for the process become higher. In the production process, the critical dimension of the final-site metal interconnection layer is defined by using a patterning process of two adjacent metal lines, and in ideal cases, the two adjacent metal lines are equal in size, so that the minimum or optimal parity effect (PITCH WALKING) of the critical dimension of the final-site metal interconnection layer can be ensured. In the actual process, for example, due to the influence of the fluctuation of a machine, the manufacturing of a front layer and the like, the sizes of two adjacent metal wires are unequal, and after the two adjacent metal wires are transmitted to a metal interconnection layer of a final station, the parity effect of the critical dimension of the metal interconnection layer is poor, the final electrical result is influenced, and the wafer is scrapped. Disclosure of Invention In view of the above, embodiments of the present application provide a method for manufacturing a semiconductor structure and a semiconductor structure. In a first aspect, an embodiment of the application provides a manufacturing method of a semiconductor structure, which comprises the steps of providing a substrate, forming a first transfer layer on the substrate by adopting a first photoetching process, forming a side wall covering the side wall of the first transfer layer, forming an adjusting layer covering the side wall and the first transfer layer to meet the requirement that a first dimension is larger than or equal to a first preset value, wherein the first dimension is defined as the difference between the line spacing and the line width of the first transfer layer minus twice the line width of the side wall, the line width of the adjusting layer is positively correlated with the difference between the first dimension and the first preset value, removing a horizontal part of the adjusting layer and the first transfer layer by adopting a second photoetching process to form a second transfer layer, wherein the difference between the two adjacent line spacing of the second transfer layer is smaller than or equal to a second preset value, forming a groove in the substrate by taking the second transfer layer as a mask, and filling a conductive material in the groove to form an interconnection layer. In some embodiments, forming the adjustment layer to cover the sidewall and the first transfer layer to satisfy the first dimension being greater than or equal to a first preset value includes forming the adjustment layer to have a line width having a first width according to a difference between the first dimension and the first preset value belonging to a first section, or forming the adjustment layer to have a line width having a second width according to a difference between the first dimension and the first preset value belonging to a second section, wherein the first section and the second section are two different sections of a plurality of consecutive sections, the value of the first section is less than the value of the second section, and the first width is less than the second width. In some embodiments, the second dimension includes an absolute value of a difference between a line width of the sidewall minus twice a line width of the first transfer layer and a line width of the adjustment layer, wherein a ratio between the second dimension and the line width of the adjustment layer ranges from 1.0 to 1.5. In some embodiments, a second lithography etching process is used to remove the horizontal portion of the adjustment layer and the first transfer layer to form a second transfer layer, including forming a second patterned lithography layer covering the adjustment layer, sequentially removing the adjustment layer and the first transfer layer on the first transfer layer with the second patterned lithography layer as a mask, removing the second patterned lithography layer, and removing the adjustment layer on the substrate to form a second transfer layer, wherein the vertical portion of the adjustment layer and the sidewall that are not removed form the second transfer layer. In some embodiments, the vertical portion of the adjustment layer that is not removed covers the top surface of the sidewall and one of the sidewalls. In some embodiments, a substrate is provided that includes sequentially forming a target layer and a first etch stop layer, sequentially forming a hard mask layer and a second etch stop layer overlying the first etch stop layer, forming a first transfer layer on the substrate using a first photolithographic etching process that includes forming the fi