CN-121985801-A - Method for manufacturing semiconductor device

Abstract

The invention provides a manufacturing method of a semiconductor device, which comprises the steps of providing a substrate, wherein the substrate comprises a well region and the well region comprises a top doped region, depositing a first interlayer dielectric layer on the well region, forming at least one contact through hole in the first interlayer dielectric layer, forming a first lower metal layer in the first interlayer dielectric layer, depositing a second interlayer dielectric layer on the first interlayer dielectric layer, forming at least one guide hole in the second interlayer dielectric layer, and forming a first upper metal layer on the second interlayer dielectric layer, wherein the second thickness of the second interlayer dielectric layer is not greater than the first thickness of the first interlayer dielectric layer, and the first lower metal layer is electrically connected with the first upper metal layer through the first guide hole in the at least one guide hole.

Inventors

• CHEN BAIAN

Assignees

• 新唐科技股份有限公司

Dates

Publication Date

20260505

Application Date

20250704

Priority Date

20241029

Claims (10)

1. 1. A method for manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate comprises a well region, and the well region comprises a top doped region; depositing a first interlayer dielectric layer on the well region; Forming at least one contact via in the first interlayer dielectric layer; Forming a first lower metal layer in the first interlayer dielectric layer; Depositing a second interlayer dielectric layer on the first interlayer dielectric layer; Forming at least one via hole in the second interlayer dielectric layer, and Forming a first upper metal layer on the second interlayer dielectric layer, Wherein: a second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer; the first lower metal layer is electrically connected with the first upper metal layer through a first via hole in the at least one via hole, and The step of forming the first lower metal layer in the first interlayer dielectric layer includes: removing a first shallow part of the first interlayer dielectric layer through a patterning process to form a first shallow groove; Depositing a conductive material on the first interlayer dielectric layer by a deposition process to form the first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench in which the conductive material is deposited, and A top surface of the first lower metal layer and a first top surface of the first inter-layer dielectric layer are substantially coplanar by a planarization process.
2. 2. The method of claim 1, wherein the first lower metal layer is not electrically connected to the well region through the at least one contact via.
3. 3. The method of manufacturing of claim 1, wherein forming the at least one via in the second interlayer dielectric layer comprises: removing a first deep portion of the second interlayer dielectric layer by patterning process to form a first deep trench, and Conductive material is deposited in the first deep trench by a deposition process to form the first via.
4. 4. The method of manufacturing of claim 1, wherein the well region comprises a source region and a drain region, the method further comprising: and forming a second lower metal layer in the first interlayer dielectric layer, wherein the second lower metal layer is electrically connected with the source region or the drain region through a second contact through hole in the at least one contact through hole.
5. 5. The method of manufacturing of claim 4, wherein the first upper metal layer is further electrically connected to the second lower metal layer through a second via of the at least one via.
6. 6. The method of claim 4, wherein the first upper metal layer is not electrically connected to the second lower metal layer through the at least one via.
7. 7. A method for manufacturing a semiconductor device, comprising: providing a substrate, wherein the substrate comprises a well region, and the well region comprises a top doped region; depositing a first interlayer dielectric layer on the well region; Forming at least one contact via in the first interlayer dielectric layer; Forming a first lower metal layer in the first interlayer dielectric layer; Depositing a second interlayer dielectric layer on the first interlayer dielectric layer; Forming at least one via hole in the second interlayer dielectric layer, and Forming a first upper metal layer on the second interlayer dielectric layer, Wherein: a second thickness of the second interlayer dielectric layer is not greater than a first thickness of the first interlayer dielectric layer; the first lower metal layer is electrically connected with the top doped region in the well region through a first contact through hole in the at least one contact through hole, and The step of forming the first lower metal layer in the first interlayer dielectric layer includes: removing a first shallow part of the first interlayer dielectric layer through a patterning process to form a first shallow groove; Depositing a conductive material on the first interlayer dielectric layer by a deposition process to form the first lower metal layer, wherein the first lower metal layer corresponds to the first shallow trench in which the conductive material is deposited, and A top surface of the first lower metal layer and a first top surface of the first inter-layer dielectric layer are substantially coplanar by a planarization process.
8. 8. The method of claim 7, wherein the first lower metal layer is not electrically connected to the first upper metal layer through the at least one via.
9. 9. The method of manufacturing of claim 7, wherein forming the at least one contact via in the first interlayer dielectric layer comprises: removing a first deep portion of the first interlayer dielectric layer by patterning process to form a first deep trench, and Depositing a conductive material on the first interlayer dielectric layer through a deposition process to form the first contact via, wherein the first contact via corresponds to the first deep trench in which the conductive material is deposited.
10. 10. The method of manufacturing of claim 7, wherein the well region comprises a source region and a drain region, the method further comprising: And forming a second lower metal layer in the first interlayer dielectric layer, wherein the second lower metal layer is electrically connected with the source region or the drain region through a second contact through hole in the at least one contact through hole.

Description

Method for manufacturing semiconductor device Technical Field The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a high voltage semiconductor device. Background Laterally diffused metal oxide semiconductor (LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR, LDMOS) transistors are now widely used in various power integrated circuits or smart power integrated circuits. LDMOS are increasingly used in high voltage integrated circuits (e.g., 500V to 700V). In order to improve the performance and reliability of the ultra-high voltage LDMOS, the electric field distribution may need to be properly adjusted and optimized. For example, a thicker dielectric layer (inter-LAYER DIELECTRIC, ILD) may reduce the impact of high voltage on the LDMOS on-path, thereby reducing device degradation. However, a thicker ILD layer may complicate the high aspect ratio etching process even more, which may lead to higher process cost and device throughput issues. Therefore, how to effectively improve the performance and reliability of LDMOS without significantly increasing the etching complexity is a worth solving problem. Disclosure of Invention In order to solve the above-mentioned problems, the present invention provides a method for manufacturing a semiconductor device to optimize the characteristics of the semiconductor device. Embodiments of the present invention provide a method of manufacturing a semiconductor device, comprising providing a substrate (substrate), wherein the substrate comprises a well (well) region and the well region comprises a top doped (dopping) region, depositing a first inter-layer dielectric (INTERLAYER DIELECTRIC, ILD) layer over the well region, forming at least one Contact (CT) in the first inter-layer dielectric layer, forming a first lower metal layer in the first inter-layer dielectric layer, depositing a second inter-layer dielectric layer over the first inter-layer dielectric layer, forming at least one via (via) in the second inter-layer dielectric layer, and forming a first upper metal layer over the second inter-layer dielectric layer, wherein a second thickness of the second inter-layer dielectric layer is not greater than a first thickness of the first inter-layer dielectric layer, the first lower metal layer is electrically connected to the first upper metal layer through a first of the at least one of the first vias, and forming the first lower metal layer in the first inter-layer dielectric layer comprises a first via pattern, forming a first upper metal layer by a shallow trench, and planarizing the first top surface by a first process, and depositing a conductive material on the first top surface layer by a shallow trench. Optionally, the first lower metal layer is not electrically connected to the well region through the at least one contact via. Optionally, the step of forming the at least one via in the second interlayer dielectric layer includes: Removing a first deep part of the second interlayer dielectric layer through a patterning process to form a first deep trench; and depositing a conductive material in the first deep trench by a deposition process to form the first via. Optionally, the well region includes a source (source) region and a drain (drain) region, and the method further includes forming a second lower metal layer in the first interlayer dielectric layer, wherein the second lower metal layer is electrically connected to the source region or the drain region through a second contact via of the at least one contact via. Optionally, the first upper metal layer is further electrically connected to the second lower metal layer through a second via of the at least one via. Optionally, the first upper metal layer is not electrically connected to the second lower metal layer through the at least one via. Embodiments of the present invention additionally provide a method of manufacturing a semiconductor device, comprising providing a substrate (substrate), wherein the substrate comprises a well (well) region and the well region comprises a top doped (dopping) region, depositing a first inter-layer dielectric (INTERLAYER DIELECTRIC, ILD) layer over the well region, forming at least one Contact (CT) in the first inter-layer dielectric layer, forming a first lower metal layer in the first inter-layer dielectric layer, depositing a second inter-layer dielectric layer over the first inter-layer dielectric layer, forming at least one via (via) in the second inter-layer dielectric layer, and forming a first upper metal layer over the second inter-layer dielectric layer, wherein a second thickness of the second inter-layer dielectric layer is not greater than a first thickness of the first inter-layer dielectric layer, the first lower metal layer electrically connecting the top doped region in the first inter-layer dielectric layer through a first contact via in the at least one contact via, and formin