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CN-121985805-A - Semiconductor structure preparation method and semiconductor structure

CN121985805ACN 121985805 ACN121985805 ACN 121985805ACN-121985805-A

Abstract

The present disclosure relates to a semiconductor structure fabrication method and a semiconductor structure, and relates to the technical field of integrated circuits, including providing a substrate having a top surface covered with a first stack; forming at least one through hole penetrating through the first lamination, forming a first conductive structure with the top surface lower than the top surface of the dielectric lamination in the through hole, transversely etching and removing part of the dielectric lamination to obtain a groove exposing the whole top surface of the first conductive structure, removing the first sacrificial layer to form a second barrier layer at least covering the side wall of the groove, filling the groove with the second sacrificial layer to form a second lamination covering the second sacrificial layer, forming a T-shaped groove penetrating through the second lamination and with the lower part narrow and the upper part wide, removing the second sacrificial layer to obtain a target groove, and forming a third barrier layer covering the inner surface of the target groove to form the target conductive structure in the target groove. At least, the occurrence of electrical failure due to migration of metal atoms can be prevented.

Inventors

  • WANG WENZHI

Assignees

  • 合肥晶合集成电路股份有限公司

Dates

Publication Date
20260505
Application Date
20260403

Claims (10)

  1. 1. A method of fabricating a semiconductor structure, comprising: Providing a substrate with a top surface covered with a first lamination layer, wherein the first lamination layer comprises a dielectric lamination layer and a first sacrificial layer which are laminated in sequence along a direction away from the substrate; forming at least one through hole penetrating through the first laminated layer, and forming a first conductive structure in the through hole, wherein the top surface of the first conductive structure is lower than the top surface of the dielectric laminated layer, and the first conductive structure comprises a first conductive layer and a first barrier layer covering the outer side wall and the bottom surface of the first conductive layer; Laterally etching and removing part of the dielectric stack to obtain a groove exposing all top surfaces of the first conductive structure, wherein the critical dimension of the groove is related to the critical dimension of the first conductive structure; After removing the first sacrificial layer, forming a second barrier layer at least covering the side wall of the groove; forming a second lamination layer covering the second sacrificial layer after filling the groove with the second sacrificial layer; Forming a T-shaped groove penetrating through the second laminated layer, wherein the bottom surface of the T-shaped groove is positioned in the top surface of the second sacrificial layer; removing the second sacrificial layer to obtain a target groove; and forming a third barrier layer covering the inner surface of the target groove, and then forming a target conductive structure in the target groove.
  2. 2. The method of manufacturing a semiconductor structure according to claim 1, wherein the number of film layers of the second stacked layer and the first stacked layer is the same, and in the film layer sequence along the direction away from the substrate, the material of the corresponding film layers of the same film layer sequence number in the first stacked layer and the second stacked layer is the same.
  3. 3. The method of claim 1, wherein the first stack comprises a first dielectric layer, a second dielectric layer, a third dielectric layer, and a first sacrificial layer stacked in sequence in a first direction away from the top surface of the substrate; the laterally etching and removing portions of the dielectric stack includes: and (3) laterally etching and removing part of the second dielectric layer and part of the third dielectric layer to obtain grooves exposing all top surfaces of the first conductive structures, wherein the ratio of the critical dimension of the grooves to the critical dimension of the first conductive structures is R, and R is 1.05,1.1.
  4. 4. The method of claim 1, wherein the second barrier layer covers sidewalls of the recess, the second sacrificial layer covers an entire top surface of the first conductive structure exposed by the recess, the second sacrificial layer covers a portion of the dielectric stack exposed by the recess, or The second barrier layer covers the side wall of the groove, the second barrier layer covers the whole top surface of the first conductive structure exposed by the groove, and the second barrier layer covers the part of the dielectric stack exposed by the groove.
  5. 5. The method of manufacturing a semiconductor structure of claim 1, comprising at least one of the following features: the first sacrificial layer comprises a metal barrier layer; the second sacrificial layer comprises alpha-carbon and/or fluorinated amorphous carbon.
  6. 6. The method of claim 1, wherein the second sacrificial layer comprises a target carbon layer; removing the second sacrificial layer, comprising: the target carbon layer is treated and removed with a target gas comprising ozone.
  7. 7. The method of manufacturing a semiconductor structure of claim 3, wherein the first dielectric layer comprises a nitrogen doped carbide film; Forming at least one via through the first stack, comprising: dry etching the first laminated layer to obtain initial holes penetrating through the first sacrificial layer, the third dielectric layer and the second dielectric layer; And over-etching the nitrogen doped carbide film through the initial hole to obtain the through hole.
  8. 8. The preparation method of the semiconductor structure is characterized by comprising the following target process steps: a method for fabricating a semiconductor structure as defined in any one of claims 1 to 7, and And flattening the second lamination to obtain the target conductive structure with the top surface flush with the top surface of the rest second lamination.
  9. 9. The method of claim 8, wherein the target process steps are sequentially repeated a predetermined number of times.
  10. 10. A semiconductor structure, comprising: The dielectric stack comprises a dielectric stack layer, a substrate, a first conductive structure, a second conductive layer, a first barrier layer, a groove, a second barrier layer and a first electrode, wherein the dielectric stack layer is covered on the top surface of the substrate, at least one through hole penetrating through the dielectric stack layer is formed in the dielectric stack layer, the through hole is internally provided with the first conductive structure, the top surface of the first conductive structure is lower than the top surface of the dielectric stack layer, the first conductive structure comprises a first conductive layer and a first barrier layer which covers the outer side wall and the bottom surface of the first conductive layer, the dielectric stack layer is internally provided with the groove which exposes the whole top surface of the first conductive structure, and the critical dimension of the groove is related to the critical dimension of the first conductive structure; The dielectric laminated structure comprises a dielectric laminated layer, a second laminated layer and a third barrier layer, wherein the dielectric laminated layer is arranged on the top surface of the dielectric laminated layer, a T-shaped groove which penetrates through the second laminated layer and is communicated with the groove is arranged in the second laminated layer, the bottom surface of the T-shaped groove is positioned in the groove, the T-shaped groove and the groove jointly form a target groove, the inner surface of the target groove is covered with the third barrier layer, and the target groove comprises a target conductive structure.

Description

Semiconductor structure preparation method and semiconductor structure Technical Field The present disclosure relates to the field of integrated circuit manufacturing technology, and in particular, to a semiconductor structure and a method for manufacturing the same. Background With the rapid development of semiconductor technology, the requirements of the market on the integrated circuit for integration level, performance and reliability are higher and higher, so that the number and structural complexity of laminated film layers inside a chip are continuously increased, and the back-end interconnection process is more and more important in the field of chip manufacturing. In the prior process, the critical dimension of the graph is smaller, the dielectric constant of the interlayer dielectric material is lower, the void ratio is higher, the structure is loose, the resistance of the interconnection structure is increased, and even open and short circuits occur, so that the whole chip fails. Disclosure of Invention In view of the foregoing, it is desirable to provide a semiconductor structure manufacturing method and a semiconductor structure that can at least fully surround a target conductive structure with a barrier layer, prevent the occurrence of electrical failure due to metal atom migration, reduce the impedance of the target conductive structure, and reduce the occurrence probability of open or short circuits (short). According to various embodiments of the present disclosure, a first aspect of the present disclosure provides a semiconductor structure fabrication method, comprising: Providing a substrate with a top surface covered with a first lamination layer, wherein the first lamination layer comprises a dielectric lamination layer and a first sacrificial layer which are laminated in sequence along a direction deviating from the substrate; Forming at least one through hole penetrating through the first laminated layer, and forming a first conductive structure in the through hole, wherein the top surface of the first conductive structure is lower than the top surface of the dielectric laminated layer, and the first conductive structure comprises a first conductive layer and a first barrier layer covering the outer side wall and the bottom surface of the first conductive layer; Laterally etching and removing part of the dielectric stack to obtain a groove exposing all top surfaces of the first conductive structure, wherein the critical dimension of the groove is related to the critical dimension of the first conductive structure; after removing the first sacrificial layer, forming a second barrier layer at least covering the side wall of the groove; after filling the groove with the second sacrificial layer, forming a second laminated layer covering the second sacrificial layer; Forming a T-shaped groove which penetrates through the second laminated layer and is narrow at the lower part and wide at the upper part, wherein the bottom surface of the T-shaped groove is positioned in the top surface of the second sacrificial layer; Removing the second sacrificial layer to obtain a target groove; And forming a third barrier layer covering the inner surface of the target trench, and then forming a target conductive structure in the target trench. In the method for manufacturing a semiconductor structure in the above embodiment, after forming at least one through hole penetrating through the first stacked layer, a first conductive structure having a top surface lower than the top surface of the dielectric stacked layer is formed in the through hole, and the first conductive structure includes a first conductive layer and a first barrier layer covering the outer sidewall and the bottom surface of the first conductive layer, so as to form a first conductive layer surrounded by the first barrier layer and the bottom surface and the outer sidewall. The first sacrificial layer can protect the dielectric stack from damaging the dielectric stack during etching to form the via, and avoid affecting the thickness/height of the target conductive structure in the recess due to uncontrollable depth of the subsequent recess. And then, according to the depth of the required transverse etching, part of the dielectric lamination is transversely etched and removed to obtain grooves exposing all top surfaces of the first conductive structures, and the key dimensions of the grooves are related to those of the first conductive structures, so that the grooves can be ensured to expose all top surfaces of the first conductive structures, and the probability of generating current leakage channels between adjacent interconnection structures due to overlarge key dimensions of the grooves can be avoided. The depth of the lateral etching is related to the speed and the etching time of the lateral etching, and the lateral etching depth can be precisely controlled by controlling the etching time. After removing the first sacrificial lay