CN-121985807-A - Semiconductor structure manufacturing method and semiconductor structure

CN121985807ACN 121985807 ACN121985807 ACN 121985807ACN-121985807-A

Abstract

The embodiment of the application discloses a semiconductor structure manufacturing method and a semiconductor structure, comprising the steps of forming a first metal pattern on the surface of a substrate, circularly using oxygen plasma and hydrogen plasma to perform first treatment on the side wall of the first metal pattern to reduce roughness, forming a dielectric layer of a low dielectric constant material on the surface of the substrate to cover the top of the first metal pattern, forming a through hole with the bottom connected with the top of the first metal pattern on the surface of the dielectric layer, performing second treatment on the side wall of the through hole by using nitrogen free radicals to modify the surface of a low dielectric constant material on the side wall of the through hole, forming a tantalum layer on the side wall of the through hole, and filling the second metal layer electrically connected with the first metal pattern in the through hole. The embodiment of the application can reduce the risk of short circuit or open circuit, enhance the adhesion of the back-end metal interconnection and realize lower resistance and interconnection stability.

Inventors

WANG SHIJING
WANG ZHAOXIANG
HE DEQIN
WU QIAN
LIU LONG

Assignees

上海邦芯半导体科技有限公司

Dates

Publication Date: 20260505
Application Date: 20260407

Claims (10)

1. A method of fabricating a semiconductor structure, comprising: Providing a substrate; forming a first metal layer on the surface of the substrate, wherein the material of the first metal layer comprises ruthenium; Patterning the first metal layer to form a first metal pattern, wherein the side wall of the first metal pattern has a first roughness; Recycling plasmas of an oxidizing first gas and a reducing second gas, and performing first treatment on the side wall of the first metal pattern, wherein the side wall of the first metal pattern after the first treatment has a second roughness, and the second roughness is smaller than the first roughness; Forming a dielectric layer on the surface of the substrate, and covering the top of the first metal pattern, wherein the material of the dielectric layer comprises a low dielectric constant material; Forming a through hole with the bottom connected with the top of the first metal pattern on the surface of the dielectric layer; performing a second treatment on the sidewall of the via using nitrogen radicals excited by metastable particles to modify the surface of the low dielectric constant material on the sidewall of the via; Forming a tantalum layer on the side wall of the through hole after the second treatment; And filling a second metal layer electrically connected with the first metal pattern in the through hole inside the tantalum layer.
2. The method according to claim 1, wherein the first treatment is performed by sequentially circulating the plasma of the oxidizing first gas and the plasma of the reducing second gas a plurality of times or sequentially circulating the plasma of the reducing second gas and the plasma of the oxidizing first gas a plurality of times and using the plasma of the reducing second gas the last time of the circulating.
3. The method according to claim 1, wherein the ruthenium material on the surface of the protrusions on the side wall of the first metal pattern is preferentially oxidized by using the plasma of the oxidizing first gas to generate volatile ruthenium tetroxide, at least a part of the protrusions are removed, the side wall of the first metal pattern is smoothed, the ruthenium dioxide on the side wall of the first metal pattern is reduced by using the plasma of the reducing second gas to reset the surface chemical state, and the roughness of the side wall of the first metal pattern is reduced by recycling the plasma of the oxidizing first gas and the plasma of the reducing second gas a plurality of times during the first process.
4. The method of manufacturing a semiconductor structure according to claim 1, wherein each time the first gas is used, a flow rate is 50sccm to 200sccm, a temperature is 10 ℃ to 125 ℃, a pressure is 5mTorr to 20mTorr, a source power is 500W to 1000W, a bias power is 0W to 30W, and a time is 5s to 30s, and/or each time the second gas is used, a flow rate is 100sccm to 300sccm, a temperature is 10 ℃ to 80 ℃, a pressure is 10mTorr to 30mTorr, a source power is 800W to 1500W, a bias power is 0W to 30W, and a time is 10s to 60s.
5. The method of claim 1, wherein the first gas comprises oxygen and/or the second gas comprises hydrogen.
6. The method of claim 1, wherein the second treatment is performed to react nitrogen radicals with bond bonds on the surface of the low-k material on the sidewall of the via hole and form a nitrogen-rich surface layer, and wherein the surface of the low-k material on the sidewall of the via hole is modified to improve adhesion and interface diffusion barrier properties of the surface of the low-k material on the sidewall of the via hole, and/or wherein the low-k material comprises a silicon-based low-k material.
7. The method for manufacturing the semiconductor structure according to claim 1, wherein the nitrogen free radical is obtained by exciting nitrogen by using helium metastable particles and filtering charged particles in the nitrogen free radical, the helium metastable particles are obtained by exciting helium and filtering the charged particles in the helium metastable particles, and when the second treatment is performed, the flow of the helium is 1000 sccm-9000 sccm, the flow of the nitrogen is 1:1-10:1, the temperature is 50 ℃ to 200 ℃, the source power is 1W-100W, the pressure is 10 mTorr-1000 mTorr, the time is 5 s-300 s, ion filtering is turned on, and the bias power is turned off.
8. The method of claim 1, further comprising performing a third treatment on the surface of the tantalum layer to reduce the surface state density using hydrogen radicals excited by metastable particles after forming the tantalum layer.
9. The method for manufacturing a semiconductor structure according to claim 8, wherein the hydrogen radicals are obtained by exciting hydrogen gas by using helium metastable particles, filtering out charged particles in the hydrogen gas, wherein the helium metastable particles are obtained by exciting helium gas, filtering out the charged particles in the helium gas, adding argon gas into the hydrogen gas during the third treatment, adjusting the concentration of the hydrogen gas, wherein the flow rate of the helium gas is 1000 sccm-2000 sccm, the flow rate of a mixed gas of the hydrogen gas and the argon gas is helium gas=0.1:1-2:1, the flow rate of the hydrogen gas is argon gas=1:1-1:3, the temperature is 100 ℃ to 200 ℃, the source power is 100 w-500 w, the pressure is 10 mTorr-1000 mTorr, the time is 5 s-300 s, and the bias power is turned on for ion filtering.
10. A semiconductor structure obtained by the method of manufacturing a semiconductor structure according to any one of claims 1-9.

Description

Semiconductor structure manufacturing method and semiconductor structure Technical Field The present application relates to the field of semiconductor processing technology, and in particular, to a semiconductor structure manufacturing method and a semiconductor structure. Background Conventional "dual damascene" processes face multiple limits in the shrinking age where effective resistance and RC delay are difficult to continue to decrease, and patterning and filling are difficult at high aspect ratios. For this reason, the industry explores the evolution path of the "subtractive" patterning process (depositing metal and then etching the pattern) for the most critical, densely patterned underlying metal layers (e.g., M1, M2), while the well-established "damascene" additive patterning process is still used for the upper via and pattern-wide metal layers. At present, metal ruthenium (Ru) is a preferred material for a bottom metal layer suitable for a 'subtractive process', but after ruthenium is etched, the problem of poor side wall roughness often exists, the risk of short circuit or open circuit is easily caused, and the overlay accuracy is affected. In addition, a copper (Cu) metal via for interconnection generally needs to use a combination of tantalum nitride (TaN) and tantalum (Ta) as a diffusion barrier layer, but with an increase in pattern density of an underlying metal layer, the diameter size of the via is also continuously reduced, which causes that the thickness of the diffusion barrier layer is larger and larger than the specific gravity of the entire Cu metal via diameter, and the specific gravity of the resistance of the diffusion barrier layer is also larger and larger in the entire via hole, which becomes a main cause that the back-end contact resistance and RC delay are difficult to continuously decrease. Therefore, there is a need to develop a process that significantly ameliorates the above-mentioned problems. Disclosure of Invention The present application is directed to a method for fabricating a semiconductor structure and a semiconductor structure thereof. In order to achieve the above purpose, the technical scheme of the application is as follows: according to a first aspect of the present application, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: Providing a substrate; forming a first metal layer on the surface of the substrate, wherein the material of the first metal layer comprises ruthenium; Patterning the first metal layer to form a first metal pattern, wherein the side wall of the first metal pattern has a first roughness; Recycling plasmas of an oxidizing first gas and a reducing second gas, and performing first treatment on the side wall of the first metal pattern, wherein the side wall of the first metal pattern after the first treatment has a second roughness, and the second roughness is smaller than the first roughness; Forming a dielectric layer on the surface of the substrate, and covering the top of the first metal pattern, wherein the material of the dielectric layer comprises a low dielectric constant material; Forming a through hole with the bottom connected with the top of the first metal pattern on the surface of the dielectric layer; performing a second treatment on the sidewall of the via using nitrogen radicals excited by metastable particles to modify the surface of the low dielectric constant material on the sidewall of the via; Forming a tantalum layer on the side wall of the through hole after the second treatment; And filling a second metal layer electrically connected with the first metal pattern in the through hole inside the tantalum layer. In some embodiments, the first treatment is performed by sequentially recycling the plasma of the first oxidizing gas and the plasma of the second reducing gas a plurality of times, or sequentially recycling the plasma of the second reducing gas and the plasma of the first oxidizing gas a plurality of times, and using the plasma of the second reducing gas the last time the recycling was performed. In some embodiments, the reduction of roughness of the sidewalls of the first metal pattern is achieved by preferentially oxidizing ruthenium material on the surfaces of the protrusions present on the sidewalls of the first metal pattern using a plasma of the oxidizing first gas to generate volatile ruthenium tetroxide to remove at least a portion of the protrusions, smoothing the sidewalls of the first metal pattern, reducing ruthenium dioxide present on the sidewalls of the first metal pattern using a plasma of the reducing second gas to reset the surface chemistry, and recycling the plasma of the oxidizing first gas and the plasma of the reducing second gas multiple times while the first treatment is performed. In some embodiments, the first gas is used at a flow rate of 50sccm to 200sccm, a temperature of 10 ℃ to 125 ℃, a pressure of 5mTorr to 20mTorr,