CN-121985809-A - Semiconductor device and forming method

CN121985809ACN 121985809 ACN121985809 ACN 121985809ACN-121985809-A

Abstract

The present disclosure provides semiconductor devices and methods of forming. The dielectric layer of the semiconductor device may be treated using an oxidation treatment process to adjust the dielectric constant of the dielectric layer. For example, an Etch Stop Layer (ESL) in an interconnect layer of a semiconductor device may be formed of a high dielectric constant (high k) dielectric material that provides for etch selectivity of the ESL relative to other dielectric layers in the interconnect layer. A recess may be formed through the ESL and through the dielectric layer, and a conductive structure may be formed in the recess. Before forming the conductive structure, an oxidation treatment operation may be performed to oxidize the exposed ends of the ESL in the recess. The oxidation treatment may reduce the dielectric constant of the ends of the ESL, which may make the ends of the ESL less susceptible to current leakage from tunneling, hot carrier injection, and/or thermionic emission.

Inventors

LIN YUFENG
CAI YUXUAN
XIAO YUTING
WU HONGMING
Hong Minxiu
YANG ZIXUAN
LIN WEIRONG
ZHANG ZHIWEI
CAI MINGXING

Assignees

台湾积体电路制造股份有限公司

Dates

Publication Date: 20260505
Application Date: 20250627
Priority Date: 20250407

Claims (10)

1. A semiconductor device, comprising: A device layer; An integrated circuit device in the device layer, and An interconnect layer over the integrated circuit device, the interconnect layer comprising: A plurality of interlayer dielectric (ILD) layers; A plurality of Etch Stop Layers (ESLs) interposed with the plurality of ILD layers; A plurality of metallization structures in the plurality of ILD layers; a plurality of the interconnect structures, Wherein a first interconnect structure of the plurality of interconnect structures extends vertically through a first ESL of the plurality of ESLs to couple two or more metallization structures of the plurality of metallization structures, Wherein a second interconnect structure of the plurality of interconnect structures extends vertically through a second ESL of the plurality of ESLs to couple the integrated circuit device to the interconnect layer, an Wherein the first dielectric constant of the second ESL is greater than the second dielectric constant of at least one of the plurality of ILD layers, and An oxide region laterally between the second ESL and a sidewall of the second interconnect structure, Wherein the third dielectric constant of the oxide region is less than the first dielectric constant of the second ESL.
2. The semiconductor device of claim 1, wherein a bottom surface of the second interconnect structure is coupled to a top surface of a source/drain contact of the integrated circuit device; Wherein the second ESL comprises silicon nitride (Si x N y ), and Wherein the oxide region comprises silicon oxide (SiO x ).
3. The semiconductor device of claim 1, wherein a first portion of a top surface of an oxide region of the oxide regions is in contact with an ILD layer of the plurality of ILD layers that is above the second ESL, and Wherein a second portion of the top surface of the oxide region is in contact with the second interconnect structure.
4. The semiconductor device of claim 3, wherein the oxide region is laterally between the second ESL and the first section of the sidewall of the second interconnect structure; wherein a second section of a sidewall of the second interconnect structure is laterally adjacent to the ILD layer over the second ESL, and Wherein the sidewall of the second interconnect structure includes a stepped section that transitions between the first section and the second section.
5. The semiconductor device of claim 1, wherein a bottom surface of the second interconnect structure is located at a lower vertical position in the semiconductor device than a bottom surface of the second ESL and a bottom surface of an oxide region of the oxide regions.
6. The semiconductor device of claim 1, wherein a bottom surface of the second interconnect structure is coupled to a top surface of a gate structure of the integrated circuit device; Wherein the second ESL comprises silicon nitride (Si x N y ), and Wherein the oxide region comprises silicon oxide (SiO x ).
7. The semiconductor device of claim 1, wherein a first band gap of a first material of the oxide region is less than a second band gap of a second material of the second ESL.
8. The semiconductor device of claim 1, wherein an oxygen concentration in a portion of the oxide region at an interface between the oxide region and a sidewall of the interconnect structure is greater than a nitrogen concentration in the portion of the oxide region at the interface between the oxide region and the sidewall of the interconnect structure.
9. A method, comprising: recesses are formed in an Etch Stop Layer (ESL) of an interconnect layer of a semiconductor device and in a dielectric layer, Wherein the dielectric layer is over the ESL, and Wherein the ESL is over a contact structure and a gate structure of an integrated circuit device in a device layer of the semiconductor device; an oxidation treatment operation is performed on the end of the ESL exposed in the recess, Wherein the oxidation treatment operation causes an oxide region to form on the end of the ESL, an Wherein the first material of the oxide region and the second material of the ESL are different materials having different band gaps, and A conductive structure of the interconnect layer is formed in the recess.
10. A method, comprising: The semiconductor device is provided into a process chamber of a plasma tool, Wherein the material of the cover of the processing chamber comprises a metal oxide material or a metal-containing ceramic material, Wherein the semiconductor device comprises recesses in an Etch Stop Layer (ESL) and in a dielectric layer of an interconnect layer of the semiconductor device, Wherein the dielectric layer is over the ESL, Wherein the dielectric layer and the ESL comprise different dielectric materials, an Wherein the ESL is over a contact structure and a gate structure of an integrated circuit device in a device layer of the semiconductor device, and A plasma treatment operation is performed to treat the end of the ESL exposed in the recess, Wherein the plasma treatment operation causes an oxide region to form on the end of the ESL, Wherein the first dielectric constant of the oxide region is less than the second dielectric constant of the ESL, and Wherein the material of the lid of the process chamber resists damage to the lid by the plasma processing operation.

Description

Semiconductor device and forming method Technical Field The present disclosure relates to semiconductor devices and methods of forming. Background Interconnect layers (sometimes referred to as back-end-of-line (BEOL) regions) are regions of a semiconductor device that include multiple layers of conductive structures arranged to carry signals and/or provide power distribution throughout the semiconductor device. The multi-layer conductive structure may include various vertically arranged interconnect structure (e.g., via) layers and metallization structure (e.g., trench, conductive line, trace) layers. Disclosure of Invention In one aspect, embodiments of the application provide a semiconductor device comprising a device layer, an integrated circuit device in the device layer, and an interconnect layer over the integrated circuit device, the interconnect layer comprising a plurality of inter-layer dielectric (ILD) layers, a plurality of Etch Stop Layers (ESLs) interposed with the plurality of ILD layers, a plurality of metallization structures in the plurality of ILD layers, a plurality of interconnect structures, wherein a first interconnect structure of the plurality of interconnect structures extends vertically through a first ESL of the plurality of ESLs to couple two or more metallization structures of the plurality of metallization structures, wherein a second interconnect structure of the plurality of interconnect structures extends vertically through a second ESL of the plurality of ESLs to couple the integrated circuit device to the interconnect layer, and wherein a first dielectric constant of the second ESL is greater than a second dielectric constant of at least one ILD layer of the plurality of ILD layers, and an oxide region is located laterally between the second ESL and a sidewall of the second interconnect structure, wherein a third dielectric constant of the oxide region is less than the first dielectric constant of the second ESL. In another aspect, embodiments of the present application provide a method comprising forming a recess in an Etch Stop Layer (ESL) and in a dielectric layer of an interconnect layer of a semiconductor device, wherein the dielectric layer is over the ESL and wherein the ESL is over a contact structure and a gate structure of an integrated circuit device in a device layer of the semiconductor device, performing an oxidation treatment operation on an end of the ESL exposed in the recess, wherein the oxidation treatment operation causes an oxide region to be formed on the end of the ESL, and wherein a first material of the oxide region and a second material of the ESL are different materials having different bandgaps, and forming a conductive structure of the interconnect layer in the recess. In yet another aspect, embodiments of the present application provide a method comprising providing a semiconductor device into a process chamber of a plasma tool, wherein a material of a lid of the process chamber comprises a metal oxide material or a metal-containing ceramic material, wherein the semiconductor device comprises an Etch Stop Layer (ESL) of an interconnect layer of the semiconductor device and a recess in a dielectric layer, wherein the dielectric layer is over the ESL, wherein the dielectric layer and the ESL comprise different dielectric materials, and wherein the ESL is over a contact structure and a gate structure of an integrated circuit device in a device layer of the semiconductor device, and performing a plasma processing operation to process an end of the ESL exposed in the recess, wherein the plasma processing operation causes an oxide region to form on the end of the ESL, wherein a first dielectric constant of the oxide region is less than a second dielectric constant of the ESL, and wherein the material of the lid of the process chamber resists damage to the lid by the plasma processing operation. Drawings Various aspects of the embodiments of the disclosure may be best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that the various structures are not drawn to scale according to industry standard practices. In fact, the dimensions of the various structures may be arbitrarily increased or reduced for clarity of discussion. Fig. 1A-1C are illustrations of a portion of an example semiconductor device described herein. Fig. 2 is an illustration of an example implementation of elemental composition of a portion of a semiconductor device as described herein. Fig. 3A-3E are illustrations of example implementations of forming a semiconductor device described herein. Fig. 4A-4H are illustrations of example implementations of forming source/drain interconnect structures described herein. Fig. 5A-5H are illustrations of example implementations of forming a gate interconnect structure as described herein. Fig. 6A-6H are illustrations of example implementations of forming source/drain intercon