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CN-121985810-A - Three-dimensional chip and electronic equipment

CN121985810ACN 121985810 ACN121985810 ACN 121985810ACN-121985810-A

Abstract

The embodiment of the application provides a three-dimensional chip and electronic equipment, relates to the technical field of chips, and aims to solve the problem that more redundant interfaces are required to be arranged in the existing three-dimensional chip. The three-dimensional chip comprises a first bare chip and a second bare chip, wherein the first bare chip comprises a first storage device and a redundant storage device, the second bare chip comprises a first input and output port and a multiplexer array, and the multiplexer array is used for selectively conducting the first input and output port with the first storage device through a first interconnection interface or conducting the first input and output port with the redundant storage device through a redundant interconnection interface. Because the memory device on the first bare chip is connected with the multiplexer array on the second bare chip through the interconnection interface, when the multiplexer array is used for repairing the memory device, the interconnection interface between the memory device and the multiplexer array can be repaired without additionally arranging a large number of redundant interconnection interfaces, and winding resources are saved.

Inventors

  • LU JINLEI
  • Ethan Rosen

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260505
Application Date
20241030

Claims (14)

  1. 1. A three-dimensional chip, characterized in that the three-dimensional chip comprises a first die, a second die and a plurality of interconnect interfaces, the first die and the second die being stacked in a thickness direction, the first die and the second die being coupled by the plurality of interconnect interfaces; the first die includes a first memory device and a redundant memory device, the plurality of interconnect interfaces including a first interconnect interface and a redundant interconnect interface; The second die includes a first input-output port and a multiplexer array electrically connected to the first input-output port, the multiplexer array selectively connecting the first input-output port to the first memory device via the first interconnect interface or connecting the first input-output port to the redundant memory device via the redundant interconnect interface.
  2. 2. The three-dimensional chip of claim 1, wherein the multiplexer array is configured to select to conduct the first input output port with the first memory device through the first interconnect interface in the absence of a failure of the first interconnect interface and the first memory device; the multiplexer array is further configured to select to conduct the first input output port to the redundant memory device through the redundant interconnect interface in the event of a failure of the first interconnect interface or the first memory device.
  3. 3. The three-dimensional chip of claim 2, wherein the multiplexer array comprises a first multiplexer comprising a fixed end, a first select end, and a second select end; The fixed end of the first multiplexer is connected with the first input/output port, the first selection end of the first multiplexer is connected with the first storage device through the first interconnection interface, and the second selection end of the first multiplexer is connected with the redundant storage device through the redundant interconnection interface; the first multiplexer selectively conducts a first selection end of the first multiplexer and a fixed end of the first multiplexer under the condition that the first interconnection interface and the first storage device have no faults; The first multiplexer selects to turn on a second selection terminal of the first multiplexer and a fixed terminal of the first multiplexer in case of a failure of the first interconnection interface or the first memory device.
  4. 4. The three-dimensional chip of claim 1, wherein the first die further comprises a second memory device, the second die further comprises a second input-output port, the multiplexer array further electrically connected to the second input-output port, the plurality of interconnect interfaces further comprising a second interconnect interface; the multiplexer array is used for selectively conducting the first input/output port with the first storage device through the first interconnection interface, conducting the second input/output port with the second storage device through the second interconnection interface, or conducting the first input/output port with the redundant storage device through the redundant interconnection interface, and conducting the second input/output port with the first storage device through the first interconnection interface.
  5. 5. The three-dimensional chip of claim 4, wherein in the absence of a failure of the second interconnect interface and the second memory device, the multiplexer array is configured to conduct the first input output port to the first memory device through the first interconnect interface and to conduct the second input output port to the second memory device through the second interconnect interface; and under the condition that the second interconnection interface or the second storage device fails, the multiplexer array is used for conducting the first input/output port with the redundant storage device through the redundant interconnection interface and conducting the second input/output port with the first storage device through the first interconnection interface.
  6. 6. The three-dimensional chip of claim 4, wherein the multiplexer array comprises a first multiplexer, a second multiplexer, each comprising a fixed end, a first select end, and a second select end; The fixed end of the first multiplexer is connected with the first input/output port, the first selection end of the first multiplexer is connected with the first storage device through the first interconnection interface, and the second selection end of the first multiplexer is connected with the redundant storage device through the redundant interconnection interface; The fixed end of the second multiplexer is connected with the second input/output port, the first selection end of the second multiplexer is connected with the second storage device through the second interconnection interface, the second selection end of the second multiplexer is connected with the first storage device through the first interconnection interface, the first multiplexer selectively conducts the first selection end of the first multiplexer and the fixed end of the first multiplexer when the second interconnection interface and the second storage device are free from faults, and the second multiplexer selectively conducts the first selection end of the second multiplexer and the fixed end of the second multiplexer, and the first multiplexer conducts the second selection end of the first multiplexer and the fixed end of the second multiplexer when the second interconnection interface or the second storage device is faulty.
  7. 7. The three-dimensional chip of any one of claims 1-6, wherein the first die comprises any one of a static random access memory die, a dynamic random access memory die, and a flash memory die.
  8. 8. The three-dimensional chip of any one of claims 1-7, wherein the interconnect interface comprises a first terminal disposed on the first die and a second terminal disposed on the second die, the first terminal being coupled to the second terminal in a manner that includes at least one of hybrid bonding and micro-nano bonding.
  9. 9. A die comprising a first input-output port and a multiplexer array electrically connected to the first input-output port, the multiplexer array for selectively coupling the first input-output port to a first memory device in the first die via a first interconnect interface or coupling the first input-output port to a redundant memory device in the first die via a redundant interconnect interface.
  10. 10. The die of claim 9, wherein the multiplexer array is to select to conduct the first input output port with the first memory device through the first interconnect interface in the absence of a failure of the first interconnect interface and the first memory device; the multiplexer array is further configured to select to conduct the first input output port to the redundant memory device through the redundant interconnect interface in the event of a failure of the first interconnect interface or the first memory device.
  11. 11. The die of claim 9, further comprising a second input-output port, the multiplexer array further electrically connected to the second input-output port; The multiplexer array is used for selectively conducting the first input/output port with the first storage device in the first die through the first interconnection interface, conducting the second input/output port with the second storage device in the first die through the second interconnection interface, or conducting the first input/output port with the redundant storage device in the first die through the redundant interconnection interface, and conducting the second input/output port with the first storage device in the first die through the first interconnection interface.
  12. 12. The die of claim 11, wherein the multiplexer array is to conduct the first input output port with the first memory device through the first interconnect interface and the second input output port with the second memory device through the second interconnect interface in the absence of a failure of the second interconnect interface and the second memory device; and under the condition that the second interconnection interface or the second storage device fails, the multiplexer array is used for conducting the first input/output port with the redundant storage device through the redundant interconnection interface and conducting the second input/output port with the first storage device through the first interconnection interface.
  13. 13. The die is characterized by comprising a first memory device and a redundant memory device, wherein the first memory device is coupled with a multiplexer array in a second die through a first interconnection interface; the multiplexer array is used for selectively conducting a first input/output port in the second die with the first memory device through the first interconnection interface or conducting the first input/output port with the redundant memory device through a redundant interconnection interface.
  14. 14. An electronic device, comprising a circuit board and the three-dimensional chip according to any one of claims 1 to 8, wherein the three-dimensional chip is electrically connected to the circuit board.

Description

Three-dimensional chip and electronic equipment Technical Field The present application relates to the field of chip technologies, and in particular, to a three-dimensional chip and an electronic device. Background Three-dimensional stacked chips typically employ interconnect interfaces to implement signal interconnection between die (die) and die, for example, the interconnect interfaces include hybrid bonding (hybrid bonding), micro-nano bonding (micro-bump), and the like, and the interconnect interfaces are characterized by high density and small pitch, so as to meet requirements of increasing the number of interconnects and increasing bandwidth. The interconnection interface is a key medium for realizing the connection of the bare chips, the quality of the chips can be directly influenced by the yield of the interconnection interface, and the yield of the three-dimensional stacked chips can be improved by setting redundancy to repair the faults of the interconnection interface. The three-dimensional stacked chip comprises a plurality of bare chips, wherein the bare chips can be divided into a control bare chip and a storage bare chip according to functions, and the storage devices in the storage bare chip also have yield problems, and the method for repairing the faults of the storage devices is that redundant devices and repair logic are added into the storage bare chip, and after the positions of the defective storage devices are obtained through testing, the defective storage devices are replaced by the redundant devices through the repair logic. The problem of yield of memory die and the problem of yield of interconnect interface are both applied to three-dimensional stacked chips, and it is therefore desirable to provide a technique capable of repairing the defects of memory die and the defects of interconnect interface. Disclosure of Invention The embodiment of the application provides a three-dimensional chip and electronic equipment, which are used for solving the problem that more redundant interfaces are required to be arranged in the existing three-dimensional memory chip. The technical scheme adopted by the application is as follows: In a first aspect, a three-dimensional chip is provided, the three-dimensional chip comprises a first bare chip, a second bare chip and a plurality of interconnection interfaces, the first bare chip and the second bare chip are stacked in the thickness direction, the first bare chip and the second bare chip are coupled through the plurality of interconnection interfaces, the first bare chip comprises a first storage device and a redundant storage device, the plurality of interconnection interfaces comprise the first interconnection interfaces and the redundant interconnection interfaces, the second bare chip comprises a first input and output port and a multiplexer array, the multiplexer array is electrically connected with the first input and output port, and the multiplexer array is used for selectively conducting the first input and output port to the first storage device through the first interconnection interfaces or conducting the first input and output port to the redundant storage device through the redundant interconnection interfaces. In the three-dimensional chip provided by the embodiment of the application, the repair of the fault memory device can be realized by combining the multiplexer array with the redundant memory device, and the multiplexer array is arranged on the second bare chip, and the memory device on the first bare chip is connected with the multiplexer array on the second bare chip through the interconnection interface, so that when the memory device is repaired by using the multiplexer array, the fault of the interconnection interface between the memory device and the multiplexer array can be repaired, the fault repair of the interconnection interface is realized by using the repair logic of the memory device, a large number of redundant interconnection interfaces are not required to be additionally arranged, and the winding resource is saved. In one possible implementation, the multiplexer array is configured to select to conduct the first input/output port to the first memory device through the first interconnect interface in the event of a failure of the first interconnect interface and the first memory device, and to select to conduct the first input/output port to the redundant memory device through the redundant interconnect interface in the event of a failure of the first interconnect interface or the first memory device. So that it can be repaired by switching redundancy in case of failure of the interconnect interface or of a memory device connected to the interconnect interface. In one possible implementation, the multiplexer array includes a first multiplexer including a fixed end, a first selection end and a second selection end, the fixed end of the first multiplexer is connected to the first input/output port, the first