CN-121985811-A - Chip structure, chip stacking structure, manufacturing method of chip stacking structure and electronic equipment

Abstract

The embodiment of the application provides a chip structure, a chip stacking structure, a preparation method of the chip stacking structure and electronic equipment, relates to the technical field of semiconductors, and is used for reducing resistance-capacitance delay. The chip stacking structure comprises a first chip structure and a second chip structure which are arranged in a stacked mode and are electrically connected. The first chip structure comprises a first active layer, a first wiring layer and a second wiring layer which are sequentially stacked, and the second wiring layer is arranged on one side of the first wiring layer close to the second chip structure. The first wiring layer comprises a first dielectric layer and a first metal wiring located in the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal wiring located in the second dielectric layer, and the line width of the second metal wiring is larger than that of the first metal wiring. The first chip structure further comprises a first signal line positioned on the second wiring layer, and the line width of the first signal line is larger than that of the first metal wiring. The second chip structure comprises a second active layer, a third wiring layer and a fourth wiring layer which are sequentially stacked.

Inventors

• LIU ZHE
• HUANG SHUMAN
• YANG FAN

Assignees

• 华为技术有限公司

Dates

Publication Date

20260505

Application Date

20241030

Claims (16)

1. 1. A chip stack structure, characterized by comprising: a first chip structure and a second chip structure which are stacked; the first chip structure is electrically connected with the second chip structure; The first chip structure comprises a first active layer, a first wiring layer and a second wiring layer which are sequentially stacked, wherein the second wiring layer is arranged on one side of the first wiring layer close to the second chip structure, the first wiring layer comprises a first dielectric layer and a first metal wiring positioned in the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal wiring positioned in the second dielectric layer, and the line width of the second metal wiring is larger than that of the first metal wiring; The first chip structure further comprises a first signal line, wherein the first signal line is positioned on the second wiring layer, and the line width of the first signal line is larger than that of the first metal wiring; the second chip structure comprises a second active layer, a third wiring layer and a fourth wiring layer which are sequentially stacked, wherein the fourth wiring layer is arranged on one side, close to the first chip structure, of the third wiring layer, and the fourth wiring layer is electrically connected with the second wiring layer.
2. 2. The chip stacking structure as recited in claim 1, wherein, The third wiring layer comprises a third dielectric layer and a third metal wiring positioned in the third dielectric layer, and the fourth wiring layer comprises a fourth dielectric layer and a fourth metal wiring positioned in the fourth dielectric layer, wherein the line width of the fourth metal wiring is larger than that of the third metal wiring; The second chip structure further comprises a second signal line, wherein the second signal line is located on the fourth wiring layer, and the line width of the second signal line is larger than that of the third metal wiring.
3. 3. The chip stack structure according to claim 2, further comprising a first connection portion and a second connection portion, wherein the first connection portion and the second connection portion each penetrate through the second wiring layer and the fourth wiring layer, wherein a first end of the second signal line is connected to the first connection portion, and wherein a second end of the second signal line is connected to the second connection portion.
4. 4. The chip stack structure according to claim 2 or 3, wherein a line width of the first signal line and a line width of the second signal line are equal.
5. 5. The chip stack structure according to any one of claims 2 to 4, wherein the chip stack structure includes a plurality of the first signal lines and a plurality of the second signal lines, and a pitch between adjacent ones of the first signal lines is equal to a pitch between adjacent ones of the second signal lines.
6. 6. The chip stack structure according to claim 5, wherein the number of the first signal lines is equal to the number of the second signal lines.
7. 7. The chip stack structure according to any one of claims 2 to 6, wherein projections of the first signal lines on the first wiring layer and projections of the second signal lines on the first wiring layer are alternately arranged.
8. 8. The chip stack structure according to claim 7, wherein a projection of the first signal line on the first wiring layer is a first projection, a projection of the second signal line on the first wiring layer is a second projection, a first space is provided between the second projections on one side adjacent to the first projection, a second space is provided between the second projections on the other side adjacent to the first projection, and the first space is equal to the second space.
9. 9. The chip stack structure according to any one of claims 2 to 6, wherein a projection of the first signal line onto the first wiring layer and a projection of the second signal line onto the first wiring layer coincide.
10. 10. The chip stack structure according to any one of claims 1 to 9, wherein a line width of the first signal line is smaller than or equal to a line width of the second metal wiring.
11. 11. The chip stack structure according to any one of claims 1-10, further comprising a transmitting end and a receiving end, wherein the transmitting end and the receiving end are electrically connected to the first signal line, respectively, and wherein the transmitting end and the receiving end are both located in the first active layer of the first chip structure.
12. 12. A chip structure, comprising: the first active layer, the first wiring layer and the second wiring layer are sequentially stacked; The first wiring layer comprises a first dielectric layer and a first metal wiring positioned in the first dielectric layer, and the second wiring layer comprises a second dielectric layer and a second metal wiring positioned in the second dielectric layer, wherein the line width of the second metal wiring is larger than that of the first metal wiring; and the first signal line is positioned on the second wiring layer, and the line width of the first signal line is larger than that of the first metal wiring.
13. 13. An electronic device comprising the chip stack structure of any one of claims 1-11 or the chip structure of claim 12 and a printed circuit board, wherein the chip structure or the chip stack structure and the printed circuit board are electrically connected.
14. 14. A method of fabricating a chip stack structure, comprising: Forming a first active layer, a first wiring layer and a second wiring layer which are sequentially stacked; the first wiring layer comprises a first dielectric layer and a first metal wiring positioned in the first dielectric layer, and the second wiring layer comprises a second dielectric layer and a second metal wiring positioned in the second dielectric layer, wherein the line width of the second metal wiring is larger than that of the first metal wiring; forming a first signal line in the second wiring layer, wherein the line width of the first signal line is larger than that of the first metal wiring; Forming a second chip structure, wherein the second chip structure comprises a second active layer, a third wiring layer and a fourth wiring layer which are sequentially stacked; and electrically connecting the second wiring layer and the fourth wiring layer.
15. 15. The method of claim 14, wherein the third wiring layer comprises a third dielectric layer and a third metal wiring within the third dielectric layer, wherein the fourth wiring layer comprises a fourth dielectric layer and a fourth metal wiring within the fourth dielectric layer, and wherein the fourth metal wiring has a line width greater than a line width of the third metal wiring; forming the second chip structure further includes: and forming a second signal line in the fourth wiring layer, wherein the line width of the second signal line is larger than that of the third metal wiring.
16. 16. A method of manufacturing a chip structure, comprising: Forming a first active layer, a first wiring layer and a second wiring layer which are sequentially stacked; the first wiring layer comprises a first dielectric layer and a first metal wiring positioned in the first dielectric layer, and the second wiring layer comprises a second dielectric layer and a second metal wiring positioned in the second dielectric layer, wherein the line width of the second metal wiring is larger than that of the first metal wiring; And forming a first signal line in the second wiring layer, wherein the line width of the first signal line is larger than that of the first metal wiring.

Description

Chip structure, chip stacking structure, manufacturing method of chip stacking structure and electronic equipment Technical Field The present application relates to the field of semiconductor technologies, and in particular, to a chip structure, a chip stacking structure, a method for manufacturing the same, and an electronic device. Background With the development of electronic technology, the continuous functions of electronic devices are enriched and comprehensive, so that the evolution iteration requirement of higher-order chips is increased, the integration level of chips is continuously increased, chips for realizing different functions are integrated in the electronic devices, the integration requirement of chips on integrated circuits in the electronic devices is increased, and multi-chip integration and encapsulation become a trend. However, as the integration of chips increases, new challenges are presented to both the rate of signal transmission within the chip and the bandwidth density of signal transmission. Disclosure of Invention The embodiment of the application provides a chip structure, a chip stacking structure, a preparation method of the chip stacking structure and electronic equipment. In order to achieve the above purpose, the application adopts the following technical scheme: In a first aspect of an embodiment of the present application, a chip stack structure is provided, including a first chip structure and a second chip structure that are stacked and electrically connected. The first chip structure comprises a first active layer, a first wiring layer and a second wiring layer which are sequentially stacked, and the second wiring layer is arranged on one side of the first wiring layer close to the second chip structure. The first wiring layer comprises a first dielectric layer and a first metal wiring located in the first dielectric layer, the second wiring layer comprises a second dielectric layer and a second metal wiring located in the second dielectric layer, and the line width of the second metal wiring is larger than that of the first metal wiring. The first chip structure further comprises a first signal line positioned on the second wiring layer, and the line width of the first signal line is larger than that of the first metal wiring. The second chip structure comprises a second active layer, a third wiring layer and a fourth wiring layer which are sequentially stacked, and the fourth wiring layer is arranged on one side, close to the first chip structure, of the third wiring layer. The fourth wiring layer is electrically connected with the second wiring layer The chip stacking structure provided by the embodiment of the application is characterized in that the first chip structure and the second chip structure are electrically connected through the second wiring layer and the fourth wiring layer. The first wiring layer is used for connecting the circuit structures in the first chip structure, and the second wiring layer is used for providing power for the circuit structures in the first chip structure. The line width of the second metal wiring in the second wiring layer is larger than that of the first metal wiring in the first wiring layer so as to meet the power supply requirement of the circuit structure in the first chip structure. Therefore, compared with the resistance-capacitance delay of the first metal wiring, the resistance-capacitance delay of the second metal wiring is lower, so that the first signal wire is arranged in the second wiring layer, the resistance-capacitance delay in signal transmission in the first signal wire can be reduced, the interconnection rate of the chip stacking structure is improved, and the performance of the chip stacking structure is improved. In one possible implementation, the third wiring layer includes a third dielectric layer and a third metal wiring located in the third dielectric layer, and the fourth wiring layer includes a fourth dielectric layer and a fourth metal wiring located in the fourth dielectric layer, and a line width of the fourth metal wiring is greater than a line width of the third metal wiring. The second chip structure further comprises a second signal line positioned on the fourth wiring layer, and the line width of the second signal line is larger than that of the third metal wiring. Thus, the third wiring layer is used for connecting the circuit structures in the second chip structure, and the fourth wiring layer is used for providing power for the circuit structures in the second chip structure. The line width of the fourth metal wiring in the fourth wiring layer is larger than the line width of the third metal wiring in the third wiring layer so as to meet the power supply requirement of the circuit structure in the second chip structure, compared with the resistance-capacitance delay of the third metal wiring, the resistance-capacitance delay of the fourth metal wiring is lower, therefore, the second si