CN-121985816-A - Chip packaging structure and computing equipment

CN121985816ACN 121985816 ACN121985816 ACN 121985816ACN-121985816-A

Abstract

The embodiment of the specification provides a chip packaging structure and electronic equipment, the clock and signal interconnection of adjacent core grains are realized through N layers of interconnection metal layers positioned on one side of the core grain layers, compared with the scheme of realizing interconnection between the core grains based on an intermediate layer, the chip packaging structure can greatly shorten the length of signal lines, effectively promote the number of signal lines which can be arranged, and relieve the limitation of interconnection density and bandwidth bottleneck, thereby realizing the purpose of meeting the requirements of mass parallel communication between the core grains. And the number of N layers of interconnection metal layers is inversely related to the width of the open hole area, the height of the N layers of interconnection metal layers is positively related to N, and through the constraint, the width of the open hole area and the number of the interconnection metal layers can be reasonably designed on the basis of meeting the interval requirements between the interconnection metal layers and between signal lines, and in addition, the signal crosstalk between the signal lines is shielded through shielding lines, so that the normal transmission of data and clock signals is ensured.

Inventors

DOU QIANG
WANG YAO
MA ZHUO

Assignees

飞腾信息技术有限公司

Dates

Publication Date: 20260505
Application Date: 20251223

Claims (10)

1. A chip package structure, comprising: the core particle layer comprises a plurality of core particles, wherein the core particles comprise a sending unit and a receiving unit, one side surface of each core particle comprises an opening area, the core particle further comprises a plurality of first through holes distributed in the opening area, and the first through holes expose a first connecting end of the core particle; the post process structure is positioned at one side of the core particle layer and comprises N layers of interconnection metal layers, the interconnection metal layers comprise a plurality of signal wires and a plurality of shielding wires, the signal wires are connected with the first connecting end through the first through holes, and the shielding wires are positioned between at least part of adjacent signal wires; The signal lines comprise a plurality of signal line groups, each signal line group comprises a signal transmission line and a clock transmission line, the signal transmission lines are used for connecting the signal output end of a first core particle with the signal receiving end of a second core particle, and the first core particle is adjacent to the second core particle; the clock transmission line is used for connecting the clock output end of the first core particle and the clock receiving end of the second core particle.
2. The chip package structure of claim 1, wherein the transmitting unit comprises a first D flip-flop, a first transmit buffer and a second transmit buffer, the interconnect metal layer further comprises a data transmit pad and a clock transmit pad, wherein, The signal end of the first D trigger is used for receiving data to be transmitted, the clock end of the first D trigger is used for receiving a clock signal generated by the first core particle, the output end of the first D trigger is connected with the input end of the first transmission buffer, the output end of the first transmission buffer is connected with the data transmission bonding pad, and one side of the data transmission bonding pad, which is far away from the first transmission buffer, is connected with one end of a signal transmission line; the input end of the second transmitting buffer is used for receiving the clock signal generated by the first core particle, the output end of the second transmitting buffer is connected with the clock transmitting bonding pad, and the clock transmitting bonding pad is also connected with one end of the clock transmission line.
3. The chip package structure according to claim 2, wherein a data offset of the data to be transmitted from the signal output terminal of the die to the data transmission pad is less than or equal to one quarter of the clock signal.
4. The chip package structure of claim 2, wherein the receiving unit comprises a second D flip-flop, a first receiving buffer and a second receiving buffer, the interconnect metal layer further comprises a data receiving pad and a clock receiving pad, wherein, The data receiving pad is used for connecting one end of the signal transmission line far away from the first core particle, and is also used for connecting the input end of the first receiving buffer; the clock receiving pad is used for being connected with one end of the clock transmission line far away from the first core particle, the clock receiving pad is also used for being connected with the input end of the second receiving buffer, the output end of the second receiving buffer is connected with the clock end of the second D trigger, the driving capacity of the first receiving buffer is smaller than that of the first sending buffer and smaller than that of the second sending buffer, and the driving capacity of the second receiving buffer is smaller than that of the first sending buffer and smaller than that of the second sending buffer.
5. The chip package structure of claim 4, wherein the receiving unit further comprises a first isolation unit and a second isolation unit, wherein, The input end of the first isolation unit is connected with the output end of the second D trigger, the input end of the second isolation unit is connected with the output end of the second receiving buffer, and the enabling ends of the first isolation unit and the second isolation unit are used for receiving the isolation unit enabling signals of the second core particles.
6. The chip package structure of claim 1, wherein N is inversely related to the width of the open area, and the height of the N interconnect metal layer is positively related to N.
7. The chip package structure according to any one of claims 1 to 6, wherein the shield wire is suspended; Or alternatively The core particle also comprises a plurality of second through holes positioned in the open hole area, wherein the second through holes expose the grounding end of the core particle; The shielding wire is electrically connected with the grounding end through the second via hole.
8. The chip package structure according to any one of claims 1 to 6, wherein in at least one of the interconnection metal layers, a line width of at least a portion of the signal lines is greater than or equal to 2 times a minimum line width, and a pitch of at least a portion of the signal lines is greater than or equal to 2 times a minimum pitch.
9. The chip package structure according to any one of claims 1 to 6, wherein the signal line extends along a first direction or extends along a second direction, and the first direction intersects the second direction.
10. A computing device according to any one of claims 1 to 9, comprising a chip package structure.

Description

Chip packaging structure and computing equipment Technical Field The present disclosure relates to the field of chip packaging technologies, and in particular, to a chip packaging structure and a computing device. Background With the continuous progress of semiconductor process nodes, the number of functional modules and transistors that can be integrated by a single System on Chip (SoC) is continuously increasing. However, limited to the maximum exposure field size of the lithography machine, there is a clear upper limit to the physical area of a single Die (Die) that can be fabricated under a single reticle. This fundamental limitation makes many high performance computing, artificial intelligence training, and high-end graphics processing applications requiring ultra-large silicon areas impractical to implement with monolithically integrated system-on-chip. In order to break through the limitation of the area of a single chip and improve the effective silicon area and the system performance in the package, advanced packaging technology has been developed rapidly. Among them, the 2.5-dimensional packaging technology based on an Interposer (Interposer) has become a mainstream scheme for realizing heterogeneous integration of multiple chips in the industry. In this approach, a plurality of functional chips (or "die", chiplet) are mounted side-by-side on a silicon-based or redistribution layer (RDL) interposer, with lateral electrical interconnection between the chips being achieved through metal wiring layers within the interposer, which itself is connected to the underlying package substrate through bumps (e.g., microbumps, μbump). However, the signal density of the interconnection based on the interposer is severely limited by the size and pitch of the microbumps, and the requirement of mass-parallel communication between the die cannot be met. Disclosure of Invention The embodiment of the specification provides a chip packaging structure and computing equipment, so as to achieve the purpose of meeting the requirements of large-scale parallel communication among core particles. In order to achieve the technical purpose, the embodiment of the specification provides the following technical scheme: In a first aspect, an embodiment of the present specification provides a chip package structure, including: the core particle layer comprises a plurality of core particles, wherein the core particles comprise a sending unit and a receiving unit, one side surface of each core particle comprises an opening area, the core particle further comprises a plurality of first through holes distributed in the opening area, and the first through holes expose a first connecting end of the core particle; The post process structure is positioned at one side of the core particle layer and comprises N layers of interconnection metal layers, wherein the interconnection metal layers comprise a plurality of signal wires and a plurality of shielding wires, the signal wires are connected with the first connecting end through the first via holes, and the shielding wires are positioned between at least part of adjacent signal wires; The signal lines comprise a plurality of signal line groups, each signal line group comprises a signal transmission line and a clock transmission line, the signal transmission lines are used for connecting the signal output end of a first core particle with the signal receiving end of a second core particle, and the first core particle is adjacent to the second core particle; the clock transmission line is used for connecting the clock output end of the first core particle and the clock receiving end of the second core particle. In a second aspect, an embodiment of the present specification further provides a computing device including a chip packaging structure as described in any one of the above. As can be seen from the above technical solutions, the chip package structure provided in the embodiments of the present disclosure sets a post-process structure on one side of the core layer, where the post-process structure includes N interconnection metal layers, and the interconnection metal layers may be film layers made based on a post-process (BEOL). The first connection ends of the core particles are exposed by the first through holes, the first through holes can comprise a signal output end, a clock output end, a signal receiving end and a clock receiving end, wherein the signal output end and the clock output end are electrically connected with the sending unit, the signal receiving end and the clock receiving end are electrically connected with the receiving unit, the interconnection metal layer can comprise a plurality of signal wires and a plurality of shielding wires, the signal wires are connected with the first connection ends through the first through holes, the shielding wires are positioned between at least part of adjacent signal wires, the plurality of signal wires comprise a plurality of grou