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CN-121985819-A - Substrate of embedded power device and manufacturing method thereof

CN121985819ACN 121985819 ACN121985819 ACN 121985819ACN-121985819-A

Abstract

The invention discloses a substrate with a power device embedded therein and a manufacturing method thereof, which relate to the technical field of semiconductors and are used for solving the problem of how to improve the heat dissipation performance of the substrate comprising the power device. The substrate of the embedded power device comprises a core plate structure, a chip and a heat and electric conduction structure, wherein the core plate structure comprises a through groove, and the chip and the heat and electric conduction structure are embedded in the through groove. The heat and electricity conducting structure is located on at least one side of the chip and is distributed with the chip at intervals. The first insulating layer is filled in a gap between any two of the chip, the heat and electric conduction structure and the inner wall of the through groove. The heat conduction property of the heat conduction and electric conduction structure is larger than that of the first insulating layer. The circuit layer structure is formed on the surfaces of the chip, the heat and electric conduction structure and the core plate structure. The circuit layer that circuit layer structure includes is connected with chip, heat conduction electric conduction structure, and first electrode layer sets up in two circuit layer structures one side that deviates from first insulating layer. The heat dissipation structure is arranged on one surface of the at least one first electrode layer, which is away from the circuit layer structure, and is connected with the circuit layer structure.

Inventors

  • YU ZHONGYAO

Assignees

  • 中国科学院微电子研究所

Dates

Publication Date
20260505
Application Date
20260204

Claims (10)

  1. 1. A substrate for a buried power device, comprising: A core plate structure including a through groove penetrating the core plate structure along a thickness direction of the core plate structure; The chip is embedded in the through groove; the heat conduction and electric conduction structure is embedded in the through groove, is positioned on at least one side of the chip along the direction perpendicular to the thickness of the core plate structure, and is distributed with the chip at intervals; the chip comprises a chip, a heat conduction and electric conduction structure, a first insulating layer, a first insulation layer, a second insulating layer, a first insulation layer and a second insulation layer, wherein the first insulating layer is positioned in the through groove; The circuit layer structure comprises a circuit layer and a second insulating layer, wherein the second insulating layer is provided with a metallized blind hole, and the circuit layer is connected with the chip and the heat and electric conduction structure through the metallized blind hole; The first electrode layers are respectively arranged on one sides of the two circuit layer structures, which are away from the first insulating layer, and the first electrode layers comprise a plurality of first electrodes which are distributed at intervals along the length direction of the circuit layer structures; The heat dissipation structure is arranged on one surface of at least one first electrode layer, which is away from the circuit layer structure, and is connected with the circuit layer structure through a gap between the first electrodes.
  2. 2. The substrate of the embedded power device according to claim 1, wherein the substrate comprises at least two chips which are distributed at intervals, the heat and electric conduction structures and the chips are alternately distributed along the length direction of the core plate structure, and the heat and electric conduction structures are positioned between the two chips and are used for connecting two adjacent chips in series; the lengths of the heat and electric conduction structures positioned on two sides of the chip are L1 along the width direction of the core plate structure, the maximum distance between the end parts of two adjacent chips is L2, and L1 is larger than L2.
  3. 3. The substrate for a buried power device of claim 1, wherein, The thickness of the heat and electricity conducting structure is equal to that of the core plate structure; the thickness of the chip is equal to that of the core plate structure; the heat and electricity conducting structure comprises a first surface, a second surface and a plurality of side surfaces, wherein the first surface and the second surface are opposite in the thickness direction of the heat and electricity conducting structure, the side surfaces are located between the first surface and the second surface, and the side surfaces comprise chamfer surfaces.
  4. 4. The substrate of a buried power device according to claim 1, wherein said heat dissipating structure comprises: The circuit layer structure comprises a first electrode layer, a second electrode layer, a third insulating layer, a first insulating layer and a second insulating layer, wherein the first electrode layer is arranged on one surface of the circuit layer structure, which is away from the circuit layer structure, the third insulating layer is connected with the circuit layer structure through a gap between the first electrodes, and the heat conduction performance of the third insulating layer is larger than that of the first insulating layer and the second insulating layer; the first metal layer is arranged on one surface of the third insulating layer, which is away from the first electrode layer; and the radiator is arranged on one surface of the first metal layer, which is away from the third insulating layer.
  5. 5. The substrate of the embedded power device of claim 4, further comprising a second electrode layer, wherein a plurality of second electrode layers are arranged on one surface of the first electrode layer, which is away from the circuit layer structure, along the length direction of the first electrode layer; The substrate further comprises a second metal layer, a plurality of second metal layers are arranged on one surface, away from the radiator, of the first metal layer along the length direction of the first metal layer, and the first metal layer and the second metal layer are pressed with the third insulating layer.
  6. 6. The substrate of the embedded power device of claim 5, wherein the ratio of the depth to the width of the second electrode layer is greater than or equal to 1:1, the depth direction of the second electrode layer is consistent with the thickness direction of the first electrode layer, and the width direction of the second electrode layer is consistent with the length direction of the first electrode layer; The ratio of the depth to the width of the second metal layer is greater than or equal to 1:1, the depth direction of the second metal layer is consistent with the thickness direction of the first metal layer, and the width direction of the second metal layer is consistent with the length direction of the first metal layer; The depth value range of the second electrode layer is 5 micrometers to 50 micrometers, and the depth value range of the second metal layer is 5 micrometers to 50 micrometers; The shape of the longitudinal section of the second electrode layer or the second metal layer is a closed graph formed by a circle, a quadrangle, a triangle or an arc and a line segment.
  7. 7. The substrate of a buried power device according to claim 5 or 6, wherein a pitch between said second electrode layer and said second metal layer on the same side of said core structure is a second distance; The third insulating layer between the second electrode layer and the second metal layer is a second interval insulating layer, and the second distance is larger than the standard thickness of the second interval insulating layer.
  8. 8. A method for manufacturing a substrate of an embedded power device is characterized in that, Providing an inner layer structure, wherein the inner layer structure comprises a core plate structure, a chip, a heat and electricity conducting structure, a first insulating layer, a circuit layer structure and a first electrode layer; The chip and the heat conduction and electric conduction structure are embedded in the through groove, the heat conduction and electric conduction structure is located on at least one side of the chip along the direction perpendicular to the thickness of the core plate structure, the heat conduction and electric conduction structure and the chip are distributed at intervals, the first insulating layer is located in the through groove, the first insulating layer is filled in a gap between any two of the chip, the heat conduction and electric conduction structure and the inner wall of the through groove, the heat conduction performance of the heat conduction and electric conduction structure is larger than that of the first insulating layer, the circuit layer structure is formed on two surfaces of the chip, the two surfaces of the heat conduction and electric conduction structure and the two surfaces of the core plate structure along the thickness direction, the circuit layer structure comprises a circuit layer and a second insulating layer, the circuit layer is connected with the chip and the heat conduction and electric conduction structure through the metallized blind holes, the first insulating layer is arranged on the two surfaces of the circuit layer and the first insulating layer and the second insulating layer respectively extends along the length direction; Forming a seed layer over the inner layer structure; forming a first mask material layer over the seed layer; Processing the first mask material layer to form a first pattern mask, wherein the first pattern mask exposes a part of the seed layer positioned on the first electrode layer; Forming a second electrode material layer on the exposed seed layer, wherein the second electrode material layer and the exposed seed layer form a second electrode layer, and the second electrode material layer is connected with the first electrode layer through the seed layer; Removing the first pattern mask and the seed layer under the first pattern mask; and a heat dissipation structure is formed on one surface of the first electrode layer and the second electrode layer, which is away from the circuit layer structure, and the heat dissipation structure is connected with the circuit layer structure through a gap between the first electrodes.
  9. 9. The method of manufacturing a substrate for a buried power device according to claim 8, wherein forming a heat dissipation structure on the first electrode layer and the second electrode layer comprises: Forming a third insulating layer on one surface of the first electrode layer and the second electrode layer, which is away from the circuit layer structure, wherein the third insulating layer is connected with the circuit layer structure through a gap between the first electrodes, and the heat conduction performance of the third insulating layer is larger than that of the first insulating layer and the second insulating layer; Forming a first metal layer and a second metal layer on one surface of the third insulating layer, which is away from the first electrode layer, wherein a plurality of second metal layers are arranged on one surface of the first metal layer, which is towards the third insulating layer, along the length direction of the first metal layer; And forming a radiator on one surface of the first metal layer, which is away from the third insulating layer.
  10. 10. The method of manufacturing a substrate for a buried power device according to claim 9, wherein forming a first metal layer and a second metal layer on a side of the third insulating layer facing away from the first electrode layer comprises: Providing a supporting plate; bonding glue is pressed on one surface of the supporting plate; pressing a first metal layer on the bonding adhesive; Forming a second mask material layer on one surface of the first metal layer, which is away from the bonding adhesive; processing the second mask material layer to form a second graph mask, wherein the second graph mask exposes at least part of the first metal layer; Forming a second metal layer on the first metal layer exposed outside the second pattern mask; defining a structure including the support plate, the bonding adhesive, the first metal layer and the second metal layer as a laminated structure; Laminating the laminated structure on the third insulating layer, wherein the second metal layer faces the third insulating layer; and performing de-bonding treatment on the laminated structure, and removing the supporting plate and the bonding adhesive.

Description

Substrate of embedded power device and manufacturing method thereof Technical Field The invention relates to the technical field of semiconductors, in particular to a substrate of an embedded power device and a manufacturing method thereof. Background Along with the requirements of power management systems of new energy automobiles, data centers, photovoltaics and other industries on power electronic devices, the requirements are higher. The third-generation semiconductor materials represented by silicon carbide (SiC) and gallium nitride (GaN) have the advantages of large forbidden bandwidth, high breakdown voltage, high thermal conductivity, high switching speed, strong radiation resistance and the like, and are widely valued in new energy automobiles, data centers and photovoltaic industries. Traditional packages (such as TO (Transistor Outline, translation is transistor package), SMD (Surface Mounted Devices, translation is surface mount device), QFN (Quad Flat No-LEADS PACKAGE, translation is square Flat No-lead package), LGA (LAND GRID ARRAY, translation is grid array package) and the like) face high parasitic inductance of the system, poor signal quality and insufficient heat dissipation capacity, so that junction temperature is too high TO meet new product requirements. The power device is embedded in the substrate to form a highly integrated power module, so that the interconnection distance is greatly shortened, the thermal resistance of a heat dissipation interface is reduced, and the packaging size is reduced, thereby reducing parasitic parameters of signal transmission, improving the signal transmission quality, improving the heat dissipation efficiency, improving the thermal performance and improving the reliability. Therefore, high-power devices are embedded in substrates to form high-density integrated and miniaturized packages, and are widely paid attention to the industry. Because the power supply voltage of the power supply management module of the new energy and the network server is up to 800V or even 1200V, the normal working temperature of the power supply management module is about 100 ℃, and the heat management system of the power supply management module needs very high heat dissipation capability to ensure the normal operation of the power device. Therefore, how to improve the heat dissipation performance of the substrate including the power device is a technical problem to be solved in the current industry. Disclosure of Invention The invention aims to provide a substrate with a power device embedded therein and a manufacturing method thereof, which are used for improving the heat dissipation performance of the substrate comprising the power device. In order to achieve the above object, in a first aspect, the present invention provides a substrate of an embedded power device. The substrate of the embedded power device comprises a core plate structure, a chip, a heat conduction and electric conduction structure, a first insulating layer, a circuit layer structure, a first electrode layer and a heat dissipation structure. The core plate structure includes a through groove penetrating the core plate structure along a thickness direction of the core plate structure. The chip and the heat and electric conduction structure are embedded in the through groove, and the heat and electric conduction structure is positioned on at least one side of the chip along the direction perpendicular to the thickness of the core plate structure, and the heat and electric conduction structure and the chip are distributed at intervals. The first insulating layer is positioned in the through groove, and the first insulating layer is filled in a gap between any two of the chip, the heat and electric conduction structure and the inner wall of the through groove. The heat conduction property of the heat conduction and electric conduction structure is larger than that of the first insulating layer. The circuit layer structure is formed on two surfaces of the chip, two surfaces of the heat and electric conduction structure and two surfaces of the core plate structure along the thickness direction. The circuit layer structure comprises a circuit layer and a second insulating layer, wherein the second insulating layer is provided with a metallized blind hole, and the circuit layer is connected with the chip and the heat conduction and electric conduction structure through the metallized blind hole. The first electrode layers are respectively arranged on one sides of the two circuit layer structures, which are away from the first insulating layer, along the length direction of the circuit layer structures, and each first electrode layer comprises a plurality of first electrodes which are distributed at intervals. The heat dissipation structure is arranged on one surface of at least one first electrode layer, which is away from the circuit layer structure, and is connected with the circuit layer structure through a