CN-121985828-A - Photoelectric system-in-package module based on silicon adapter plate and life prediction method

CN121985828ACN 121985828 ACN121985828 ACN 121985828ACN-121985828-A

Abstract

The invention discloses a photoelectric system level packaging module based on a silicon adapter plate and a service life prediction method, and belongs to the technical field of advanced packaging and reliability of semiconductors. The method comprises the steps of configuring a silicon adapter plate into a functional microsystem carrier integrating passive devices and a sensing network, eliminating thermal resistance delay caused by a packaging medium layer, collecting deep interconnection area data in real time, optimizing power integrity by using a buried resistance-capacitance network, setting a thermal isolation groove to block transverse thermal crosstalk, constructing a physical failure model and a neural network modified dual-drive hybrid evaluation model based on multi-physical-field time sequence data, capturing and compensating nonlinear coupling damage under a dynamic voltage frequency adjustment working condition by using a long-period memory network, outputting a high-precision residual life prediction value, executing hierarchical dynamic reliability management based on a prediction result, and realizing thermal-force load balance inside a module through task migration, so that the average service life of a photoelectric system level packaging module is prolonged to the maximum extent on the premise of guaranteeing system performance.

Inventors

YANG GUOFENG
ZHANG KAIHONG
XI LIUHUA
LI XIAOQI
QIN SHIQING
SHAN XINYI
WANG JIN
LI LEILEI
SUN HUAZHEN

Assignees

江南大学
无锡中微腾芯电子有限公司

Dates

Publication Date: 20260505
Application Date: 20260408

Claims (10)

1. The photoelectric system level packaging module based on the silicon adapter plate is characterized by comprising a packaging substrate (100), the silicon adapter plate (200), an electronic system chip (300) and a photon integrated chip (400) which are arranged on the top layer from bottom to top, wherein the silicon adapter plate (200) is arranged on the upper surface of the packaging substrate (100) and is used as a core carrier for high-density interconnection, a plurality of longitudinally penetrating through silicon vias (201) are integrated in the matrix of the silicon adapter plate (200) and are used for realizing vertical electric interconnection of power supply, grounding and control signals, the electronic system chip (300) and the photon integrated chip (400) are inversely bonded on the surface of the silicon adapter plate (200) through micro bumps (500) so as to realize mechanical fixation and electric signal transmission, the matrix structure of the silicon adapter plate (200) comprises an internal monocrystalline silicon substrate and a silicon dioxide insulating layer which covers the surface layer of the monocrystalline silicon substrate, and in-situ multiple physical field sensing networks and integrated passive devices are synchronously manufactured in the monocrystalline silicon substrate by utilizing a semiconductor front channel process.
2. The packaging module of claim 1, wherein the electronic system chip (300) and the photonic integrated chip (400) are arranged side by side on the top surface of the silicon interposer (200), the multi-physical-field sensor network comprises two groups, the two groups are respectively arranged below the electronic system chip (300) and the photonic integrated chip (400) on the silicon interposer (200), and each group of multi-physical-field sensor network comprises miniature temperature sensors and stress sensors and is unevenly distributed according to different monitoring objects and types.
3. The package module of claim 2, wherein the first sensor group (202 a) is distributed in a vertical projection area of the photonic integrated chip (400) on the silicon interposer (200), wherein the micro temperature sensors are arranged in the optical waveguide coupling area and the heat-sensitive functional area for monitoring wavelength drift caused by micro temperature change, the stress sensors are arranged at edges or corners of the chip for monitoring interface shear stress caused by thermal expansion coefficient mismatch of heterogeneous materials, the second sensor group (202 b) is distributed in a vertical projection area of the electronic system chip (300) on the silicon interposer (200), the micro temperature sensors are intensively arranged under the high-power-consumption computing unit for accurately capturing transient hot spots, and the stress sensors are closely distributed around the micro bump array for monitoring stress concentration conditions in the high-density interconnection structure.
4. A packaging module according to claim 3, characterized in that the second sensor group (202 b) has a higher distribution density than the first sensor group (202 a).
5. The package module of claim 4, wherein the integrated passive devices in the silicon interposer and the sensor share a semiconductor front process, a diffusion resistor is synchronously constructed in a specific area of the substrate by using an ion implantation step for forming the sensor, and a deep trench capacitor is synchronously constructed by using a deep trench etching process for forming a through silicon via or an isolation trench and an insulating layer growth process.
6. The packaging module according to claim 5, wherein the silicon interposer (200) is provided with thermal isolation grooves (203) in a non-electrical connection region between the electronic system chip (300) and the photonic integrated chip (400), and the thermal isolation grooves (203) are deep groove structures recessed downward, and penetrate through a silicon dioxide layer on a surface layer of the silicon interposer (200) and extend into the monocrystalline silicon substrate.
7. A method for predicting the lifetime of a photovoltaic system-in-package module based on a silicon interposer, the method implementing lifetime prediction based on the package module of any one of claims 1-6, the method comprising: s1, in-situ collecting multi-source data and carrying out feature construction based on the collected data to obtain a high-dimensional system state feature vector ; S2, constructing a physical-data dual-drive hybrid life assessment model; The hybrid life assessment model comprises a physical model calculation path and a neural network correction path; Step S3, constructing a hierarchical dynamic reliability management mechanism to optimize the fusion output result of the model in the step S2; the hierarchical dynamic reliability management mechanism includes a transient thermal management mechanism based on a temperature threshold and an active load balancing mechanism based on a residual life prediction.
8. The method according to claim 7, wherein the step S1 includes: The method comprises the steps of collecting analog signals at a first sampling frequency f phys through a high-precision analog-to-digital converter by utilizing an in-situ multi-physical-field sensing network integrated in a monocrystalline silicon substrate of a silicon adapter plate, wherein the analog signals comprise N local junction temperature sequences distributed under an optical waveguide coupling area and a computing core And M thermo-mechanical stress sequences around the micro bump array ; Reading a real-time core working voltage V (t), a clock frequency f (t) and a load current density J (t) at a second sampling frequency f elec by utilizing a hardware performance counter and a power management unit which are arranged in an electronic system chip; Denoising the acquired data, and aligning the time stamps; Constructing and obtaining a high-dimensional system state feature vector at a time t , wherein, Representing the normalized local junction temperature at time t, Representative of the normalized t-time temperature change rate, Representing the normalized thermo-mechanical stress at time t, Representing the normalized core operating voltage at time t, Representing the normalized operating clock frequency of the core of the electronic system chip at the time t, Representing the normalized load current density at time t.
9. The method of claim 8, wherein the physical model calculation path of the "physical-data" dual-drive hybrid life assessment model specifically invokes a Black model to calculate electromigration damage EM based on current density and temperature, invokes a Coffin-Manson model to calculate thermal cycling damage TC based on temperature fluctuation amplitude and cycle frequency, invokes a Weibull distribution model to calculate time dependent breakdown damage TDDB based on voltage and temperature; Calculating theoretical residual life under the current working condition according to Miner linear accumulated damage theory ; The neural network correction path of the 'physical-data' dual-drive hybrid life assessment model constructs a depth time sequence prediction model based on LSTM, and the high-dimensional system state feature vector at the t moment is constructed in the step S1 For input, the hidden layer adopts a full-connection structure, and uses hyperbolic tangent and Swish activation functions to avoid gradient calculation interruption caused by non-guidance of the traditional ReLU function at zero point, and the output layer outputs a dimensionless correction coefficient Theoretical remaining life obtained by calculating path for physical model And (5) correcting to obtain the corrected residual service life RUL.
10. The method of claim 9, wherein the hierarchical dynamic reliability management mechanism performs closed-loop management on the optoelectronic system-in-package module, comprising the steps of: Acquiring a real-time temperature T real acquired by a miniature temperature sensor and a residual service life predicted value RUL output by the mixed service life evaluation model; Comparing the real-time temperature T real with a preset hot spot threshold T limit : If T real ≥T limit is determined that the system is in a transient hot air risk state, a dynamic voltage frequency adjustment strategy is directly triggered, and the local heat flux density is rapidly inhibited by reducing the working voltage or frequency of an electronic system chip in the system, so that transient overheat failure is prevented; If T real <T limit , determining that the current transient temperature of the system is in the normal range, further comparing RUL with a preset life safety threshold RUL safe : If RUL is not more than RUL safe , indicating that the system enters an aging and wearing stage, triggering a task migration strategy, and dynamically scheduling high-computation load from an aging node to other healthy nodes on the silicon adapter plate so as to realize heat-force load balance in the package; If RUL > RUL safe is monitored, the system is judged to be in a healthy state, a strategy of maintaining the current state is executed, and additional intervention is not carried out.

Description

Photoelectric system-in-package module based on silicon adapter plate and life prediction method Technical Field The invention belongs to the technical field of advanced packaging and reliability testing of semiconductors, and particularly relates to a photoelectric system level packaging module based on a silicon adapter plate and a service life prediction method. Background With the development of high-performance computing and AI, a photoelectric system-in-package module based on a silicon adapter plate becomes a mainstream packaging scheme due to the characteristics of high-density interconnection, photoelectric fusion, efficient heat dissipation and heterogeneous integration, and the high-density integration of an electronic system chip (SoC) and a photon integrated chip effectively breaks through the interconnection bottleneck, but brings serious heat flux and mechanical stress challenges. The existing Black or Coffin-Manson and other static models based on constant stress assumption (i.e. assuming that temperature, current and voltage are constant or periodically stable) are difficult to adapt to unstable working conditions caused by dynamic voltage frequency adjustment (Dynamic Voltage and Frequency Scaling, DVFS) in an AI scene, wherein BTI (Bias Temperature Instability) effect in the Black model is mainly determined by constant voltage and temperature and follows a rule of logarithmic or power law growth, transient changes of voltage in the DVFS scene can cause stress relaxation phenomenon of the BTI effect (i.e. when the voltage is reduced, the previous Vth offset part can be partially recovered instead of being added without limitation), the traditional Black model cannot capture the process, and the Coffin-Manson model focuses on stress amplitude and cycle times, and dynamic voltage frequency adjustment can influence frequency and cause power consumption fluctuation, so that the temperature of a chip shows nonlinear and frequent fluctuation, which is different from the rule of the Coffin-Manson model and the predictable thermal cycle amplitude. Some studies have shown (e.g., study one ：Papadopoulos A, Theocharides T, Michael M K. Towards optimal CMOS lifetime via unified reliability modeling and multi-objective optimization. 2011 IEEE International Symposium of Circuits and Systems (ISCAS). IEEE, 2011: 1049-1052., study two ：Coskun A K, Strong R, Tullsen D M, Rosing T S. Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors. Proceedings of the 11th International Joint Conference on Measurement and Modeling of Computer Systems, 2009: 169-180. , study three ：Moghaddam M G, Ababei C. Dynamic lifetime reliability management for chip multiprocessors[J]. IEEE Transactions on Multi-Scale Computing Systems, 2018, 4(4): 952-958.）,, omitting such dynamic nonlinear cumulative damage can result in an average time to failure (MTTF) prediction error of up to 60%, forcing the design end to reserve an excessive margin, severely restricting the release of system performance. Currently, the physical state of the core failure area inside the package has "non-observability" (i.e., the actual degradation state of the chip inside the package cannot be directly measured or monitored in real time), and many failure mechanisms exhibit complex nonlinear coupling characteristics. In the structure of the Silicon adapter plate, a heat source is tightly attached to a heat sensor, critical failure risks often occur in deep Through-Silicon Via (TSV) arrays and high-density micro bump interconnection interfaces, however, the existing monitoring means depend on chip edge sensors or surface estimation models, the chip edge sensors only can cover chip surface areas or edges to provide macroscopic temperature distribution, temperature changes captured by the sensors are often delayed from transient thermal changes in the Through-Silicon Via arrays, the surface estimation models are difficult to accurately feed back the state in the Through-Silicon Via arrays according to data acquired by the chip edge sensors, and the transient junction temperature and stress concentration states of the core interconnection areas cannot be accurately monitored due to thermal resistance delay and space average effects of heat conduction paths. More seriously, the failure mechanisms are not isolated any more, namely, local temperature rise accelerates atomic diffusion so as to exacerbate Electromigration (EM), holes and electric resistance increase caused by EM can cause Joule heat to increase, local temperature is further raised and hole growth is quickened, positive feedback can further promote local temperature, meanwhile, periodic thermo-mechanical stress generated by mismatch of thermal expansion coefficients (Coefficient of Thermal Expansion, CTE) caused by expansion or contraction of heterogeneous materials with different degrees can generate cracks at a low dielectric constant layer or in