CN-121985833-A - Overlay graph and overlay error compensation method

CN121985833ACN 121985833 ACN121985833 ACN 121985833ACN-121985833-A

Abstract

The first overlay mark comprises a plurality of first overlay marks corresponding to the first structural layer, the second overlay mark comprises at least one second overlay mark and at least one third overlay mark corresponding to the second structural layer and the third structural layer respectively, and the second overlay mark determines the quantity proportion of the second overlay mark and the third overlay mark based on the preset influence weight of the second structural layer and the third structural layer on the first structural layer respectively. The first overlay mark and the second overlay mark of the overlay pattern are formed on the first structural layer, so that the occupied area of the overlay pattern in the wafer cutting channel area can be effectively reduced, and an engineer only needs to establish a group of overlay programs, so that the processing efficiency of the wafer is further improved.

Inventors

Luo Shutong
Lin Dingqun
FANG ZHENYU
SUN HAIYANG

Assignees

重庆芯联微电子有限公司

Dates

Publication Date: 20260505
Application Date: 20251226

Claims (10)

1. The overlay graph is characterized by comprising a first overlay mark and a second overlay mark, wherein the first overlay mark and the second overlay mark are formed on a first structural layer; the first overlay mark comprises a plurality of first overlay marks corresponding to the first structural layer; the second overlay mark comprises at least one second overlay mark and at least one third overlay mark, and the second overlay mark and the third overlay mark correspond to the second structural layer and the third structural layer respectively; The second overlay mark determines the quantity ratio of the second overlay mark to the third overlay mark based on the preset influence weights of the second structural layer and the third structural layer on the first structural layer respectively.
2. The overlay graphic of claim 1, wherein the second structural layer has a preset impact weight a on the first structural layer, the third structural layer has a preset impact weight b on the first structural layer, and the number of the second overlay marks and the third overlay marks in the second overlay mark is determined based on the ratio of the preset impact weight a to the preset impact weight b; And the sum of the preset influence weight a and the preset influence weight b is 1.
3. The overlay graphic of claim 1, wherein the first overlay mark, the second overlay mark, and the third overlay mark have a width of at least 2 ± 0.5um.
4. An overlay graphic according to claim 1, wherein the second overlay mark and the third overlay mark in the second overlay mark are distributed in a plurality of rows and/or columns along the first direction and the second direction, respectively.
5. The overlay graphic of claim 4, wherein the second overlay mark and the third overlay mark are each disposed parallel to the first overlay mark.
6. The overlay graphic of claim 4, wherein the first direction is an X direction and the second direction is a Y direction.
7. The overlay pattern of claim 1, wherein the overlay pattern is located within a scribe line region of a wafer, the scribe line region having a width of 60 ± 5um, at least one group of the overlay patterns being accommodated.
8. The overlay graphic of claim 1, wherein the first structural layer, the second structural layer, and the third structural layer are stacked in sequence; The first structural layer is a lower layer, the second structural layer is an intermediate layer, and the third structural layer is an upper layer.
9. An overlay error compensation method based on the overlay pattern of any one of claims 1-8, comprising: Providing a wafer with an overlay pattern, wherein the overlay pattern comprises a first overlay mark and a second overlay mark, and the first overlay mark and the second overlay mark are formed on a first structural layer; the first overlay mark comprises a plurality of first overlay marks corresponding to the first structural layer; the second overlay mark comprises at least one second overlay mark and at least one third overlay mark, and the second overlay mark and the third overlay mark correspond to the second structural layer and the third structural layer respectively; The second overlay mark determines the quantity proportion of the second overlay mark and the third overlay mark based on the preset influence weights of the second structural layer and the third structural layer on the first structural layer respectively; and obtaining overlay error compensation data by measuring the offset of the centers of the first overlay mark and the second overlay mark in the first direction and the second direction, determining an overlay error compensation value of the next wafer batch, and compensating the exposure machine according to the overlay error compensation value.
10. The method for compensating overlay error according to claim 9, wherein the specific process of obtaining the overlay error compensation data by measuring the offset of the centers of the first overlay mark and the second overlay mark in the first direction and the second direction is as follows: The method comprises the steps of obtaining a geometric center point coordinate of a first overlay mark as a first coordinate, obtaining a geometric center point coordinate of a second overlay mark as a second coordinate, obtaining a difference value between the first coordinate and the second coordinate to obtain overlay error compensation data, and feeding the overlay error compensation data back to an exposure system to compensate wafers of the next batch.

Description

Overlay graph and overlay error compensation method Technical Field The invention belongs to the technical field of semiconductors, and particularly relates to an overlay graph and an overlay error compensation method. Background Overlay error (Overlay) refers to the correction of the process location of the next wafer lot by calculating Overlay error compensation data of the Overlay mark of the current layer and the Overlay mark of the previous layer after finishing the processing of one layer (the current layer) in the IC manufacturing process. In the semiconductor photolithography process, there are cases where layer1 (first structure layer) needs to be aligned with layer2 (second structure layer) and layer3 (third structure layer), respectively, the overlay pattern of layer2:layer1 is shown in fig. 1, the overlay pattern of layer3:layer1 is shown in fig. 2, an engineer needs to set up two sets of overlay programs to find out the coordinates of the two sets of overlay programs, which requires a long measurement time, and the two sets of overlay patterns occupy more scribe line area on the wafer, as shown in fig. 3. Therefore, how to reduce the occupied area of the overlay pattern in the dicing channel area of the wafer, and further improve the processing efficiency of the wafer, becomes a problem to be solved. Disclosure of Invention The application provides an overlay pattern and an overlay error compensation method, wherein the overlay pattern is formed on a first structural layer and comprises a first overlay mark and a second overlay mark, the first overlay mark comprises a plurality of first overlay marks corresponding to the first structural layer, the second overlay mark comprises at least one second overlay mark and at least one third overlay mark corresponding to the second structural layer and the third structural layer respectively, and the second overlay mark determines the quantity proportion of the second overlay mark and the third overlay mark based on the preset influence weight of the second structural layer and the third structural layer on the first structural layer respectively. The first overlay mark and the second overlay mark of the overlay pattern are formed on the first structural layer, so that the occupied area of the overlay pattern in the wafer cutting channel area can be effectively reduced, and an engineer only needs to establish a group of overlay programs, so that the processing efficiency of the wafer is further improved. Other objects and advantages of the present invention will be further appreciated from the technical features disclosed in the present invention. In order to achieve one or a part of or all of the above objects or other objects, the present invention provides an overlay pattern and an overlay error compensation method. An overlay pattern comprises a first overlay mark and a second overlay mark formed on a first structural layer; the first overlay mark comprises a plurality of first overlay marks corresponding to the first structural layer; the second overlay mark comprises at least one second overlay mark and at least one third overlay mark, and the second overlay mark and the third overlay mark correspond to the second structural layer and the third structural layer respectively; The second overlay mark determines the quantity ratio of the second overlay mark to the third overlay mark based on the preset influence weights of the second structural layer and the third structural layer on the first structural layer respectively. The preset influence weight of the second structural layer on the first structural layer is a, the preset influence weight of the third structural layer on the first structural layer is b, and the number of the second overlay marks and the third overlay marks in the second overlay mark is determined based on the proportion of the preset influence weight a to the preset influence weight b; And the sum of the preset influence weight a and the preset influence weight b is 1. The widths of the first overlay mark, the second overlay mark and the third overlay mark are at least 2+/-0.5 um. The second overlay marks and the third overlay marks in the second overlay mark are distributed into a plurality of rows and/or a plurality of columns along the first direction and the second direction respectively. The second overlay mark and the third overlay mark are respectively arranged in parallel with the first overlay mark. The first direction is the X direction, and the second direction is the Y direction. The overlay pattern is positioned in a dicing channel area of the wafer, the width of the dicing channel area is 60+/-5 um, and at least one group of the overlay patterns is accommodated. The first structural layer, the second structural layer and the third structural layer are sequentially stacked; The first structural layer is a lower layer, the second structural layer is an intermediate layer, and the third structural layer is an upper l