CN-121985835-A - Embedded chip packaging substrate and manufacturing method thereof

CN121985835ACN 121985835 ACN121985835 ACN 121985835ACN-121985835-A

Abstract

The invention relates to an embedded chip packaging substrate and a manufacturing method thereof, belonging to the technical field of semiconductor packaging; the manufacturing method comprises the following steps of S1, preparing a Cavity substrate, S2, embedding a chip, S3, processing blind holes, S4, electroplating a pattern, S5, forming a solder mask, S6, exposing a chip bonding pad, S7, electroplating and compensating, and S8, implanting balls. After chips are embedded in the packaging substrate, reliable electrical interconnection is established for the packaging substrate, intermetallic diffusion is prevented, corrosion resistance is improved, and a stable and solderable surface is finally provided through the process flows of copper electroplating, nickel electroplating and tin electroplating, so that the performance and long-term reliability of chip packaging are ensured.

Inventors

LAN MINGHUI
LU HAILIN
GU MIN
ZHANG LINWEI
HUANG JIANFENG

Assignees

浙江创豪半导体有限公司

Dates

Publication Date: 20260505
Application Date: 20251231

Claims (10)

1. The manufacturing method of the embedded chip packaging substrate is characterized by comprising the following steps of: s1, preparing a Cavity substrate, namely preparing a packaging substrate with a Cavity structure; s2, a chip embedding process, namely embedding a chip into the Cavity structure; s3, processing blind holes on the substrate embedded with the chip, wherein the blind holes with different apertures are processed by adopting different types of lasers; s4, a pattern electroplating process, namely performing electroless copper deposition and electroplating treatment on the blind holes to form a build-up circuit pattern layer; s5, a solder mask forming step of forming a solder mask insulating layer and performing surface treatment; s6, a chip bonding pad exposure procedure, namely exposing a circuit connection bonding pad of the chip layer; S7, electroplating compensation procedure, namely electroplating copper, nickel and tin on the substrate, and compensating tin layer thickness in the micro-aperture blind hole area; and S8, a ball planting process is completed.
2. The method for manufacturing an embedded chip package substrate according to claim 1, wherein the cavity substrate preparation process in step S1 specifically includes the following substeps: S11, performing ABF stacked film insulating layer build-up treatment on the incoming material core plate, and manufacturing a build-up circuit layer to obtain a packaging substrate; s12, performing ABF stacked film lamination and layer adding, curing and baking on the packaging substrate to obtain an insulating layer with a Cavity structure; And S13, carrying out laser on the insulating layer of the cavity structure by using CO 2 laser to form a cavity for embedding the chip, and preparing for chip embedding in a later process.
3. The method for manufacturing an embedded chip package substrate according to claim 2, wherein the step S2 specifically includes the following sub-steps: s21, after removing the glue residue on the bottom of the cavity, attaching a chip with corresponding specification; s22, embedding the chip into the laminated film, namely, sticking the chip after removing the adhesive residue at the bottom, and embedding the chip into the packaging substrate through ABF film pressing, layering and curing.
4. The method for manufacturing the embedded chip package substrate according to claim 2, wherein the blind hole processing step in the step S3 specifically includes the following sub-steps: S31, a large-aperture blind hole machining procedure, namely carrying out laser on the area outside the chip on the ABF stacking film lamination build-up layer by using CO 2 laser, and machining the large-aperture blind hole; s32, processing a micro-aperture blind hole, namely using UV laser to carry out laser on the area on the chip to process the micro-aperture blind hole; Wherein, CO 2 laser is used for processing large-aperture blind holes with aperture more than or equal to 45 mu m, and UV laser is used for processing micro-aperture blind holes with aperture of 20-25 mu m.
5. The method of manufacturing an embedded chip package substrate according to claim 4, wherein the pattern plating process in step S4 specifically includes the following sub-steps: S41, performing film pasting, exposure and development on blind holes processed by CO 2 laser and UV laser after electroless copper deposition, then performing copper electroplating, and finally performing film stripping and flash etching to obtain a build-up circuit pattern layer; S42, performing pre-solder resist treatment, film pasting exposure development and solidification on the build-up circuit pattern layer to form a solder resist insulating layer.
6. The method of manufacturing an embedded chip package substrate according to claim 1, wherein the surface treatment in step S5 is a nickel-palladium-gold surface treatment, and nickel, palladium, gold are plated on the Pad with the solder mask windowed.
7. The method for manufacturing an embedded chip package substrate according to claim 1, wherein the chip pad exposure step in the step S6 specifically includes the following substeps: S61, exposing a chip bonding pad, namely carrying out laser processing on the solder resist insulating layer by using UV laser to form a micro blind hole of 20-25 mu m, and exposing a circuit connecting bonding pad of the chip layer; S62, preparing the exposed chip connecting pad before electroplating, namely performing electroless copper plating and film pasting exposure development; s63, electroplating copper, nickel and tin, namely electroplating copper, nickel and tin on the substrate; S64, film stripping and flashing, namely after the packaging substrate finishes electroplating copper, nickel and tin, connecting a chip embedded in the packaging substrate to the electroplated nickel and tin layer through a circuit after film stripping and flashing.
8. The method for manufacturing an embedded chip package substrate according to claim 1, wherein the specific operation of tin layer thickness compensation in step S7 includes: After the first copper-nickel-tin electroplating, exposing and developing through film pasting to expose only the micro blind hole area, and then carrying out the second tin electroplating, wherein the thickness of the second tin electroplating is 3-5 mu m.
9. The method of manufacturing an embedded chip package substrate according to claim 1, wherein the ball mounting process in step S8 includes coating flux on the bonding pads, placing solder balls and performing reflow soldering.
10. An embedded chip package substrate manufactured based on the manufacturing method of the embedded chip package substrate as claimed in any one of claims 1 to 9, comprising: A core plate layer (4); The multilayer build-up circuit structure is symmetrically distributed on the upper side and the lower side of the core plate layer (4), and comprises a top build-up circuit layer (3) and a bottom build-up circuit layer (5); a build-up circuit pattern layer (2) formed on the top build-up circuit layer (3); A front solder mask layer (1) covered on the build-up circuit pattern layer (2); A back solder mask layer (6) covered under the bottom build-up circuit layer (5); The chip is embedded between the top layer build-up circuit layer (3) and the build-up circuit pattern layer (2), and is electrically connected with the build-up circuit pattern layer (2) through the blind holes; And solder balls arranged on the windowed pads of the front surface solder mask layer (1) and the back surface solder mask layer (6).

Description

Embedded chip packaging substrate and manufacturing method thereof Technical Field The invention relates to an embedded chip packaging substrate and a manufacturing method thereof, belonging to the technical field of semiconductor packaging. Background With the rapid iteration of the fields of smart phones, artificial intelligence, automatic driving and the like, semiconductor devices are rapidly developed in the directions of miniaturization, high density, high frequency and high speed. The embedded chip packaging technology can directly embed the chip into the substrate, so that the packaging volume is effectively reduced, the signal transmission path is shortened, and the embedded chip packaging technology becomes the core technology direction of the current packaging field. However, the design and processing process of the conductive structure of the internal circuit of the substrate are always key bottlenecks for restricting the improvement of the embedded package performance. First, the inherent limitations of conventional conduction schemes; the circuit conduction of the existing embedded packaging substrate mainly depends on two modes, but the defects that the circuit conduction is difficult to overcome are overcome: Laser drilling electroplating (applicable to thin core plates with plate thickness <0.15 mm); the solid X-shaped via hole is formed by laser drilling to realize interlayer conduction, but the thickness of a hole wall plating layer is uneven, the structural strength is low (easy to break), the impedance fluctuation is large during high-frequency signal transmission, and the requirements of high-frequency scenes such as 5G/6G and the like can not be met; Mechanical drilling + resin plugging mode (for thick core plates with plate thickness >0.15 mm); firstly, mechanical drilling, hole wall electroplating and resin hole plugging are carried out, the process is long, and the cost is high; the resin in the hole is not conductive and has poor current passing capability; Defects such as bubbles in holes, falling of a coating and the like easily occur, so that the probability of conducting failure is high. For example, the publication number of the prior art is CN119764180A, which discloses a manufacturing method and a structure of an embedded packaging substrate, wherein a prefabricated embedded body is embedded in a core plate opening frame to realize circuit conduction. The scheme avoids the problems of bubbles and uneven plating of the electroplating plug holes, but has the following key defects: the blind hole machining precision is low; The single laser type is adopted to process the blind holes, so that the processing efficiency of the large-aperture blind holes (more than or equal to 45 mu m) and the processing precision of the micro-aperture blind holes (20-25 mu m) cannot be considered; the connection reliability is poor; the thickness of the tin layer of the micro-aperture blind hole is 3-5 μm thinner than that of the large-aperture blind hole, so that when a chip is attached: reflow soldering is abnormal, namely a high solder ball firstly contacts with a chip bonding pad, and a low solder ball cannot contact to open a circuit; Abnormal hot-press welding, namely transverse spreading of the high tin ball under pressure and short circuit; The long-term reliability is poor, namely uneven stress of welding spots (high tin compression and low tin tension), crack initiation under temperature cycle/vibration and fatigue failure; chip warpage, namely, the serious height difference leads to the warpage of >50 mu m after chip mounting, influences the bottom filling process, and reduces the structural stability; The 3D stacking capability is weak; The traditional structure can not be wired above the chip, is difficult to realize 3D three-dimensional stacking, and restricts the further improvement of the packaging density. Environmental protection and multi-chip integration are not enough; the chip is exposed or protected insufficiently, is easily affected by external stress and moisture pollution, has high integration difficulty of chips (logic, storage and radio frequency) with different processes, and cannot meet the requirements of complex functional modules. Therefore, there is a need for a method and a structure for manufacturing an embedded chip package substrate with simple process, high blind hole processing precision and high connection reliability. Disclosure of Invention The invention aims to provide an embedded chip packaging substrate and a manufacturing method thereof, which solve the problems in the prior art. The manufacturing method of the embedded chip packaging substrate comprises the following steps: s1, preparing a Cavity substrate, namely preparing a packaging substrate with a Cavity structure; s2, a chip embedding process, namely embedding a chip into the Cavity structure; s3, processing blind holes on the substrate embedded with the chip, wherein the blind holes with diff