CN-121985837-A - Metal substrate packaging field effect transistor

CN121985837ACN 121985837 ACN121985837 ACN 121985837ACN-121985837-A

Abstract

The metal substrate packaging field effect transistor comprises a vertical field effect transistor wafer or an IGBT wafer, wherein a source electrode pad and a grid electrode pad are arranged on the bottom surface of the field effect transistor wafer, a drain electrode pad is arranged on the top surface of the wafer, the metal substrate packaging field effect transistor further comprises a metal substrate, two high-low bosses are arranged on the top surface of the metal substrate, two laminated circuit boards are provided with stepped grooves for accommodating the wafer and the bosses, the top surface of the low boss of the metal substrate is flush with a circuit layer between the substrate layers, the top surface of the high boss of the metal substrate is flush with a circuit layer on the top layer of the two laminated circuit boards, the wafer is welded on the top surface of the low boss of the metal substrate through the source electrode pad, the grid electrode pad is welded on a corresponding pad arranged on the circuit layer between the substrate layers, the wafer is placed in the hole of the upper substrate layer for accommodating the wafer, and the insulating sizing material is filled around the wafer. The encapsulation of the vertical field effect transistor or IGBT with high power density is realized by optimizing the process of the thermoelectric separation circuit board and adopting a chip wafer level encapsulation method.

Inventors

ZHAO ZHENTAO

Assignees

赵振涛

Dates

Publication Date: 20260505
Application Date: 20251123

Claims (3)

1. The metal substrate packaging field effect transistor is characterized by comprising a vertical field effect transistor wafer or an IGBT wafer, wherein a source electrode bonding pad and a grid electrode bonding pad are distributed on the bottom surface of the field effect transistor wafer, and a drain electrode bonding pad is distributed on the top surface of the wafer; the circuit board is characterized by further comprising a metal substrate, wherein the top surface of the metal substrate is provided with a high boss and a low boss, and the top surface of the high boss is plated with a circuit board surface mounting technology easy-to-weld metal layer; the circuit board also comprises two laminated circuit boards, wherein the two laminated circuit boards consist of a top layer circuit layer, an insulating upper substrate layer, an insulating lower substrate layer and a substrate interlayer circuit layer arranged between the upper substrate layer and the lower substrate layer; the two laminated circuit boards are provided with holes for accommodating wafers and bosses, the holes are stepped grooves, the lower substrate layer is provided with holes for accommodating the low bosses and the high bosses on the metal substrate, the upper substrate layer is provided with holes for accommodating the wafers and holes for accommodating the high bosses on the metal substrate, the top surfaces of the low bosses of the metal substrate are aligned with the circuit layers between the substrate layers, the top surfaces of the high bosses of the metal substrate are aligned with the circuit layers on the top layers of the two laminated circuit boards, the wafers are welded on the top surfaces of the low bosses of the metal substrate through source electrode pads, the grid electrode pads are welded on corresponding pads arranged on the circuit layers between the substrate layers, the corresponding packaging grid electrode pads are arranged on the circuit layers on the top layers of the two laminated circuit boards, the corresponding packaging grid electrode pads are in communication connection with the grid electrode pads of the wafers through holes arranged in the upper substrate layer, the wafers are arranged in the holes for accommodating the wafers, and the gaps between the wafers and the edges of the holes for accommodating the wafers are filled with insulating glue materials, and the insulating glue materials are filled around the level of the wafers.
2. The field effect transistor packaged by the metal substrate according to claim 1, wherein the field effect transistor wafers are two or more than two groups of field effect transistor wafers, the group of field effect transistor wafers are welded on the top surface of a low boss of the metal substrate through source electrode pads on the bottom surface respectively, the upper substrate layer is accommodated in a hole of the wafer, the top surface of the wafer is aligned with the top surface of a high boss of the metal substrate, the grid electrode pads of the group of field effect transistor wafers are welded on corresponding pads arranged on circuit layers between the substrate layers respectively, and are correspondingly connected with a group of packaging grid electrode pads arranged on the circuit layers on the top layer of the two laminated circuit boards through holes arranged in the upper substrate layer.
3. The metal substrate packaging field effect transistor of claim 1, wherein the field effect transistor wafer is an IGBT wafer, an emitter pad and a gate pad are arranged on the bottom surface of the IGBT wafer, and a collector pad is arranged on the top surface of the wafer.

Description

Metal substrate packaging field effect transistor Technical Field The invention relates to a packaging technology and a chip heat dissipation technology optimization and a packaging architecture design for a vertical power device, relates to a packaging technology of a field effect transistor (MOSFET) and an IGBT, and also relates to a metal processing and surface treatment technology. Background Semiconductor power devices (such as diodes, MOSFETs, HEMTs, and IGBTs) are widely used in high power electronic devices, such as power management modules, electric vehicle drive systems, and industrial motor control. Generally, the high-voltage product adopts an IGBT, and the medium-low voltage product adopts a field effect transistor (MOSFET). The third generation semiconductor materials GaN (gallium nitride) and SiC (silicon carbide) are representatives of wide forbidden band semiconductors, and the SiC (silicon carbide) manufactured power device has the remarkable characteristics of high switching speed, small chip area and the like, and is widely applied to the fields of power adapters, industrial power supplies, automobile electronics and the like. The ultra-wide band gap power devices of the fourth generation semiconductor materials mainly represented by diamond, gallium oxide and the like are also put into practical application, and the power devices manufactured by the ultra-wide band gap power devices can also work at higher temperature. The thermoelectric separation of the metal-based circuit board is a technology for independently designing a circuit signal transmission path and a heat dissipation conduction path, realizes double optimization of electrical performance and heat dissipation performance through a layered structure, and is a technology currently applied to the circuit board of a high-power electronic product. Copper substrates are generally used to achieve efficient heat dissipation. Conventional power device packages typically employ complex lead frame and metal clip structures. However, this packaging method has problems in that the process is complicated, additional metal clips and welding steps are required, the manufacturing cost and time are increased, the volume is large, and the overcurrent and heat dissipation performance are limited. Disclosure of Invention In order to solve the above-mentioned problems, the present invention provides a metal substrate packaged field effect transistor. The field effect transistor simplifies the packaging process, improves the heat radiation performance, can realize the parallel use of a plurality of vertical field effect transistor wafers or IGBT wafers, and improves the current carrying capacity. In order to achieve the technical aim, the invention provides a metal substrate packaging field effect transistor, which comprises a vertical field effect transistor wafer, wherein a source electrode bonding pad and a grid electrode bonding pad are distributed on the bottom surface of the field effect transistor wafer, and a drain electrode bonding pad is distributed on the top surface of the wafer; the semiconductor chip comprises a metal substrate, two high-low bosses, two laminated circuit boards, a thermal-compression bonding material and a bonding material, wherein the upper surface of the metal substrate is provided with a hole for accommodating a wafer and a boss, the hole is a stepped groove hole, the lower substrate layer is provided with a hole for accommodating the lower boss and the high boss on the metal substrate, the upper substrate layer is provided with a hole for accommodating the wafer and the hole for accommodating the high boss on the metal substrate, the lower boss top surface of the metal substrate is flush with a circuit layer between the substrate layers, the upper surface of the high boss of the metal substrate is flush with the circuit layer between the two laminated circuit boards, the metal substrate and the two laminated circuit boards are bonded by adopting a thermal-compression bonding material, the bonding material can adopt resin, the wafer is welded on the upper surface of the metal substrate through a bonding pad, the upper surface of the metal substrate is flush with the circuit layer between the upper substrate layer of the upper substrate through a thermal-compression bonding material, the hole is arranged on the upper surface of the substrate through a bonding pad of the metal substrate corresponding to the upper layer of the solder pad, the upper substrate is connected with the solder pad in the upper substrate through the wafer through the hole for accommodating the solder, the solder paste is arranged on the upper surface of the substrate is corresponding to the upper layer of the wafer through the bonding pad, the upper substrate is arranged on the upper layer of the bonding pad is connected with the solder pad through the solder pad, and the gap between the wafer and the hole digging edge containing the wafer